參數(shù)資料
型號： M37534M4-XXXSP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 6 MHz, MICROCONTROLLER, PDIP42
封裝： 13 X 36.72 MM, 1.78 MM PITCH, PLASTIC, SDIP-42
文件頁數(shù)： 27/56頁
文件大小： 699K
代理商： M37534M4-XXXSP
7534 Group
Rev.3.00
Oct 23, 2006
page 33 of 53
REJ03B0099-0300
Watchdog Timer
The watchdog timer gives a means for returning to a reset status
when the program fails to run on its normal loop due to a runaway.
The watchdog timer consists of an 8-bit watchdog timer H and an 8-
bit watchdog timer L, being a 16-bit counter.
Standard operation of watchdog timer
The watchdog timer stops when the watchdog timer control register
(address 003916) is not set after reset. Writing an optional value to
the watchdog timer control register (address 003916) causes the
watchdog timer to start to count down. When the watchdog timer H
underflows, an internal reset occurs. Accordingly, it is programmed
that the watchdog timer control register (address 003916) can be set
before an underflow occurs.
When the watchdog timer control register (address 003916) is read,
the values of the high-order 6-bit of the watchdog timer H, STP in-
struction disable bit and watchdog timer H count source selection bit
are read.
Initial value of watchdog timer
By a reset or writing to the watchdog timer control register (address
003916), the watchdog timer H is set to “FF16” and the watchdog
timer L is set to “FF16”.
Operation of watchdog timer H count source selection bit
A watchdog timer H count source can be selected by bit 7 of the
watchdog timer control register (address 003916). When this bit is
“0”, the count source becomes a watchdog timer L underflow signal.
The detection time is 174.763 ms at f(XIN)=6 MHz.
When this bit is “1”, the count source becomes f(XIN)/16. In this
case, the detection time is 683 s at f(XIN)=6 MHz.
This bit is cleared to “0” after reset.
Operation of STP instruction disable bit
When the watchdog timer is in operation, the STP instruction can be
disabled by bit 6 of the watchdog timer control register (address
003916).
When this bit is “0”, the STP instruction is enabled.
When this bit is “1”, the STP instruction is disabled, and an internal
reset occurs if the STP instruction is executed.
Once this bit is set to “1”, it cannot be changed to “0” by program.
This bit is cleared to “0” after reset.
Fig. 38 Block diagram of watchdog timer
Fig. 39 Structure of watchdog timer control register
XIN
Data bus
“0”
“1”
1/16
Watchdog timer H count
source selection bit
Reset
circuit
STP Instruction Disable Bit
Watchdog timer H (8)
Write “FF16” to the
watchdog timer
control register
Internal reset
RESET
Watchdog timer L (8)
STP Instruction
Write “FF16” to the
watchdog timer
control register
Watchdog timer control register(address 0039 16)
WDTCON
Watchdog timer H (read-only for high-order 6-bit)
STP instruction disable bit
0 : STP instruction enabled
1 : STP instruction disabled
Watchdog timer H count source selection bit
0 : Watchdog timer L underflow
1 : f(XIN)/16
b7
b0
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