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  • 參數(shù)資料
    型號: M37542F8GP
    元件分類: 微控制器/微處理器
    英文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP32
    封裝: 7 X 7 MM, 0.80 MM PITCH, PLASTIC, LQFP-32
    文件頁數(shù): 7/124頁
    文件大?。?/td> 1238K
    代理商: M37542F8GP
    7542 Group
    Rev.3.03
    Jul 11, 2008
    Page 102 of 117
    REJ03B0006-0303
    Timing Requirements
    Table 22 Timing requirements (1)
    (FLASH ROM version: VCC = 4.0 to 5.5V, Mask ROM version: VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
    Min.
    Typ.
    Max.
    Symbol
    Parameter
    Limits
    Unit
    Reset input “L” pulse width
    External clock input cycle time
    External clock input “H” pulse width
    External clock input “L” pulse width
    CNTR0 input cycle time
    CNTR0, INT0, INT1, CAP0, CAP1 input “H” pulse width (Note 1)
    CNTR0, INT0, INT1, CAP0, CAP1 input “L” pulse width (Note 1)
    Serial I/O1, serial I/O2 clock input cycle time (Note 2)
    Serial I/O1, serial I/O2 clock input “H” pulse width (Note 2)
    Serial I/O1, serial I/O2 clock input “L” pulse width (Note 2)
    Serial I/O1, serial I/O2 input set up time
    Serial I/O1, serial I/O2 input hold time
    tW(RESET)
    tC(XIN)
    tWH(XIN)
    tWL(XIN)
    tC(CNTR0)
    tWH(CNTR0)
    tWL(CNTR0)
    tC(SCLK1)
    tWH(SCLK1)
    tWL(SCLK1)
    tsu(RxD1–SCLK1)
    th(SCLK1–RxD1)
    2
    125
    50
    200
    80
    800
    370
    220
    100
    s
    ns
    Table 23 Timing requirements (2)
    (FLASH ROM version: VCC = 2.7 to 5.5V, Mask ROM version: VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
    Min.
    Typ.
    Max.
    Symbol
    Parameter
    Limits
    Unit
    Reset input “L” pulse width
    External clock input cycle time
    External clock input “H” pulse width
    External clock input “L” pulse width
    CNTR0 input cycle time
    CNTR0, INT0, INT1, CAP0, CAP1 input “H” pulse width (Note 1)
    CNTR0, INT0, INT1, CAP0, CAP1 input “L” pulse width (Note 1)
    Serial I/O1, serial I/O2 clock input cycle time (Note 2)
    Serial I/O1, serial I/O2 clock input “H” pulse width (Note 2)
    Serial I/O1, serial I/O2 clock input “L” pulse width (Note 2)
    Serial I/O1, serial I/O2 input set up time
    Serial I/O1, serial I/O2 input hold time
    tW(RESET)
    tC(XIN)
    tWH(XIN)
    tWL(XIN)
    tC(CNTR0)
    tWH(CNTR0)
    tWL(CNTR0)
    tC(SCLK1)
    tWH(SCLK1)
    tWL(SCLK1)
    tsu(RxD1–SCLK1)
    th(SCLK1–RxD1)
    2
    250
    100
    500
    230
    2000
    950
    400
    200
    s
    ns
    Notes 1: As for CAP0, CAP1, it is the value when noise filter is not used.
    2: In this time, bit 6 of the serial I/O1 control register (address 001A16) is set to “1” (clock synchronous serial I/O is selected).
    When bit 6 of the serial I/O1 control register is “0” (clock asynchronous serial I/O is selected), the rating values are divided by 4.
    In this time, bit 6 of the serial I/O2 control register (address 003016) is set to “1” (clock synchronous serial I/O is selected).
    When bit 6 of the serial I/O2 control register is “0” (clock asynchronous serial I/O is selected), the rating values are divided by 4.
    Notes 1: As for CAP0, CAP1, it is the value when noise filter is not used.
    2: In this time, bit 6 of the serial I/O1 control register (address 001A16) is set to “1” (clock synchronous serial I/O is selected).
    When bit 6 of the serial I/O1 control register is “0” (clock asynchronous serial I/O1 is selected), the rating values are divided by 4.
    In this time, bit 6 of the serial I/O2 control register (address 003016) is set to “1” (clock synchronous serial I/O is selected).
    When bit 6 of the serial I/O2 control register is “0” (clock asynchronous serial I/O is selected), the rating values are divided by 4.
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    參數(shù)描述
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