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參數(shù)資料
| 型號： | M37544 |
| 廠商： | Renesas Technology Corp. |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁數(shù)： | 36/68頁 |
| 文件大?。?/td> | 579K |
| 代理商： | M37544 |
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7544 Group
Rev.1.04 2004.06.08 page 36 of 66
REJ03B0012-0104Z
Fig. 44 Structure of CPU mode register
(1) Oscillation control
Stop mode
When the STP instruction is executed, the internal clock
φ
stops at
an “H” level and the X
IN
oscillator stops. At this time, timer 1 is set
to “01
16
” and prescaler 1 is set to “FF
16
” when the oscillation sta-
bilization time set bit after release of the STP instruction is “0”. On
the other hand, timer 1 and prescaler 1 are not set when the
above bit is “1”. Accordingly, set the wait time fit for the oscillation
stabilization time of the oscillator to be used. Single selected by
the timer 1 count source selection bit is connected to the input of
prescaler 1. When an external interrupt is accepted, oscillation is
restarted but the internal clock
φ
remains at “H” until timer 1
underflows. As soon as timer 1 underflows, the internal clock
φ
is
supplied. This is because when a ceramic/quartz-crystal oscillator
is used, some time is required until a start of oscillation. In case
oscillation is restarte______
ply an “L” level to the RESET pin while oscillation becomes stable.
Also, the STP instruction cannot be used while CPU is operating
by an on-chip oscillator.
Wait mode
If the WIT instruction is executed, the internal clock
φ
stops at an
“H” level, but the oscillator does not stop. The internal clock re-
starts if a reset occurs or when an interrupt is received. Since the
oscillator does not stop, normal operation can be started immedi-
ately after the clock is restarted. To ensure that interrupts will be
received to release the STP or WIT state, interrupt enable bits
must be set to “1” before the STP or WIT instruction is executed.
■
Notes on clock generating circuit
For use with the oscillation stabilization set bit after release of the
STP instruction set to “1”, set values in timer 1 and prescaler 1 af-
ter fully appreciating the oscillation stabilization time of the
oscillator to be used.
Switch of ceramic/quartz-crystal and RC oscillations
After releasing reset the operation starts by starting an on-chip os-
cillator. Then, a ceramic/quartz-crystal oscillation or an RC
oscillation is selected by setting bit 5 of the CPU mode register.
Double-speed mode
When a ceramic/quartz-crystal oscillation is selected, a double-
speed mode can be used. Do not use it when an RC oscillation is
selected.
CPU mode register
Bits 5, 1 and 0 of CPU mode register are used to select oscillation
mode and to control operation modes of the microcomputer. In or-
der to prevent the dead-lock by error-writing (ex. program
run-away), these bits can be rewritten only once after releasing re-
set. After rewriting it is disable to write any data to the bit. (The
emulator MCU “M37544RSS” is excluded.)
Also, when the read-modify-write instructions (SEB, CLB) are ex-
ecuted to bits 2 to 4, 6 and 7, bits 5, 1 and 0 are locked.
Clock division ratio, X
IN
oscillation control, on-chip oscillator con-
trol
The state transition shown in Fig. 48 can be performed by setting
the clock division ratio selection bits (bits 7 and 6), X
IN
oscillation
control bit (bit 4), on-chip oscillator oscillation control bit (bit 3) of
CPU mode register. Be careful of notes on use in Fig. 48.
Processor mode bits (Note 1)
b1 b0
0 0 Single-chip mode
0 1
1 0
1 1
0 : 0 page
1 : 1 page
Not available
b7 b0
2:
These bits are used only when a ceramic
/quartz-crystal
oscillation is selected.
Do not use these when an RC oscillation is selected.
Note 1:
The bit can be rewritten only once after releasing reset. After rewriting
it is disable to write any data to the bit. However, by reset the bit is
initialized and can be rewritten, again.
(It is not disable to write any data to the bit for emulator MCU
“M37544RSS”.)
Oscillation mode selection bit (Note 1)
0 : Ceramic/quartz-crystal oscillation
1 : RC oscillation
Clock division ratio selection bits
b7 b6
0 0 : f(
φ
) = f(X
IN
)/2 (High-speed mode)
0 1 : f(
φ
) = f(X
IN
)/8 (Middle-speed mode)
1 0 : applied from on-chip oscillator
1 1 : f(
φ
) = f(X
IN
) (Double-speed mode)(Note 2)
CPU mode register
(CPUM: address 003B
16
, initial value: 80
16
)
On-chip oscillator oscillation control bit
0 : On-chip oscillator oscillation enabled
1 : On-chip oscillator oscillation stop
X
IN
oscillation control bit
0 : Ceramic/quartz-crystal or RC oscillation enabled
1 : Ceramic/quartz-crystal or RC oscillation stop
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