參數(shù)資料
型號: M37702M2A
廠商: Mitsubishi Electric Corporation
英文描述: Single Chip 16 Bits CMOS Microcomputer(16位單片機(jī))
中文描述: 單片微機(jī)16位的CMOS(16位單片機(jī))
文件頁數(shù): 34/59頁
文件大小: 811K
代理商: M37702M2A
34
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D CONVERTER
The A-D converter is an 8-bit successive approximation converter.
Figure 43 shows a block diagram of the A-D converter and Figure
44 shows the bit configuration of the A-D control register. The fre-
quency of the A-D converter operating clock
φ
AD
is selected by the
bit 7 of the A-D control register. When bit 7 is “0”,
φ
AD
is the clock
frequency divided by 8. That is,
φ
AD
= f(X
IN
)/8. When bit 7 is “1”,
φ
AD
is the clock frequency divided by 4 and
φ
AD
is = f(X
IN
)/4. The
φ
AD
during A-D conversion must be 250 kHz minimum because
the comparator consists of a capacity coupling amplifier.
The operating mode is selected by the bits 3 and 4 of A-D control
register. The available operating modes are one-shot, repeat,
single sweep, and repeat sweep.
The bit of data direction register bit corresponding to the A-D con-
verter pin must be “0” (input mode) because the analog input port
is shared with port P7.
The operation of each mode is described below.
Fig 44
A-D control register bit configuration
Fig 43
A-D converter block diagram
Analog input selection bits
0 0 0 : Select AN
0
0 0 1 : Select AN
1
0 1 0 : Select AN
2
0 1 1 : Select AN
3
1 0 0 : Select AN
4
1 0 1 : Select AN
5
1 1 0 : Select AN
6
1 1 1 : Select AN
7
A-D operation mode selection bits
0 0 : One-shot mode
0 1 : Repeat mode
1 0 : Single sweep mode
1 1 : Repeat sweep mode
7
6
5
4
3
2
0
1
A-D control register 1
Trigger selection bit
0 : Software trigger
1 :
AD
TRG
input trigger
A-D conversion start flag
0 : Stop A-D conversion
1 : Start A-D conversion
Frequency selection flag
0 : Select f(X
IN
)/8
1 : Select f(X
IN
)/4
1E
16
Address
Data bus (even)
Selector
AN
0
AN
1
AN
2
AN
3
AN
4
AN
5
AN
6
AN
7
AD
TRG
Ladder network
Vref
Successive approximation register
Addresses
1/2
1/2
f
2
f(X
IN
)
1/2
A-D register 0 (20
16
)
A-D register 1 (22
16
)
A-D register 2 (24
16
)
A-D register 3 (26
16
)
A-D register 4 (28
16
)
A-D register 5 (2A
16
)
A-D register 6 (2C
16
)
A-D register 7 (2E
16
)
Decoder
Comparator
A-D control register
(1E
16
)
V
REF
AV
SS
A-D conversion speed selection
φ
AD
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