參數(shù)資料
型號(hào): M37736EHBGS
元件分類: 微控制器/微處理器
英文描述: 16-BIT, UVPROM, 24 MHz, MICROCONTROLLER, CQCC100
封裝: WINDOWED, CERAMIC, LCC-100
文件頁(yè)數(shù): 5/33頁(yè)
文件大?。?/td> 406K
代理商: M37736EHBGS
13
PROM VERSION OF M37736MHBXXXGP
PRELIMINARY
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
MITSUBISHI MICROCOMPUTERS
M37736EHBXXXGP
M67736EHBGS
Limits
Min.
Max.
tsu(D–E)
Data input setup time (external bus mode A)
32
ns
tsu(D–RDE)
Data input setup time (external bus mode B)
32
ns
tsu(RDY–
φ1)
___
RDY
input setup time
55
ns
tsu(HOLD–
φ1)
____
HOLD
input setup time
55
ns
th(E–D)
Data input hold time (external bus mode A)
0
ns
th(RDE–D)
Data input hold time (external bus mode B)
0
ns
th(
φ1–RDY)
___
RDY
input hold time
0ns
th(
φ1–HOLD)
____
HOLD
input hold time
0ns
Limits
Min.
Max.
tsu(P0D–E)
Port P0 input setup time
60
ns
tsu(P1D–E)
Port P1 input setup time
60
ns
tsu(P2D-E)
Port P2 input setup time
60
ns
tsu(P3D–E)
Port P3 input setup time
60
ns
tsu(P4D–E)
Port P4 input setup time
60
ns
tsu(P5D–E)
Port P5 input setup time
60
ns
tsu(P6D–E)
Port P6 input setup time
60
ns
tsu(P7D–E)
Port P7 input setup time
60
ns
tsu(P8D–E)
Port P8 input setup time
60
ns
tsu(P10D–E)
Port P10 input setup time
60
ns
th(E–P0D)
Port P0 input hold time
0ns
th(E–P1D)
Port P1 input hold time
0ns
th(E–P2D)
Port P2 input hold time
0ns
th(E–P3D)
Port P3 input hold time
0ns
th(E–P4D)
Port P4 input hold time
0ns
th(E–P5D)
Port P5 input hold time
0ns
th(E–P6D)
Port P6 input hold time
0ns
th(E–P7D)
Port P7 input hold time
0ns
th(E–P8D)
Port P8 input hold time
0ns
th(E–P10D)
Port P10 input hold time
0ns
Limits
Min.
Max.
tc
External clock input cycle time (Note 3)
40
ns
tw(H)
External clock input high-level pulse width (Note 4)
15
ns
tw(L)
External clock input low-level pulse width (Note 4)
15
ns
tr
External clock rise time
8ns
tf
External clock fall time
8ns
TIMING REQUIREMENTS (VCC = 5 V ± 10%, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz, unless otherwise noted (Note))
Notes 1. This applies when the main clock division selection bit = “0” and f(f2) = 12.5 MHz.
2. Input signal’s rise/fall time must be 100 ns or less, unless otherwise noted.
External clock input
Unit
Symbol
Parameter
Unit
Symbol
Parameter
Single-chip mode
Notes 3. When the main clock division selection bit = “1”, the minimum value of tc = 80 ns.
4. When the main clock division selection bit = “1”, values of tw(H) / tc and tw(L) / tc must be set to values from 0.45 through 0.55.
Unit
Symbol
Parameter
Memory expansion mode and microprocessor mode
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