參數(shù)資料
型號(hào)： M37736EHLHP
元件分類(lèi)： 微控制器/微處理器
英文描述： 16-BIT, OTPROM, MICROCONTROLLER, PQFP100
封裝： 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁(yè)數(shù)： 36/63頁(yè)
文件大小： 8367K
代理商： M37736EHLHP
CENTRAL PROCESSING UNIT (CPU)
7733 Group User’s Manual
2–3
2.1.1 Accumulator (Acc)
Accumulators A and B are available.
(1) Accumulator A (A)
Data processing such as calculation, data transfer, or data input/output is executed mainly through
accumulator A. It consists of 16 bits and its low-order 8 bits can also be used separately. The data
length flag (m), which is a part of the processor status register, specifies whether accumulator A is
used as a 16-bit register or an 8-bit register. When the data length is 8 bits wide, only the low-order
8 bits of accumulator A are used and the contents of the high-order 8 bits is unchanged.
(2) Accumulator B (B)
Accumulator B has the same function as accumulator A and can be used instead of accumulator A.
Note that, except for some instructions, the use of accumulator B requires more instruction bytes and
execution cycles than that of accumulator A. Accumulator B consists of 16 bits and is also affected
by the data length flag (m) just as for accumulator A.
2.1.2 Index register X (X)
Index register X consists of 16 bits and its low-order 8 bits can also be used separately. The index register
length flag (x), which is a part of the processor status register, specifies whether index register X is used
as a 16-bit register or an 8-bit register. When the index register length is 8 bits wide, only the low-order
8 bits of index register X are used and the contents of the high-order 8 bits is unchanged.
In an addressing mode where index register X is used as an index register, the address obtained by adding
the contents of index register X to the operand is accessed. In execution of a block transfer instruction
(MVP or MVN), the contents of index register X is the low-order 16 bits of the source address and the third
byte of the instruction is the high-order 8 bits of the address.
g Refer to “7700 Family Software Manual” for addressing modes.
2.1.3 Index register Y (Y)
Index register Y has the same function as index register X. Index register Y consists of 16 bits and is also
affected by the index register length flag (x) just as for index register X.
In execution of a block transfer instruction (MVP or MVN), the contents of index register Y is the low-order
16 bits of the destination address and the second byte of the instruction is the high-order 8 bits of the
address.
2.1 Central processing unit
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