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參數(shù)資料
| 型號(hào)： | M378T3253FG0-CE6 |
| 元件分類： | DRAM |
| 英文描述： | 32M X 64 DDR DRAM MODULE, 0.45 ns, DMA240 |
| 封裝： | DIMM-240 |
| 文件頁(yè)數(shù)： | 9/20頁(yè) |
| 文件大?。?/td> | 382K |
| 代理商： | M378T3253FG0-CE6 |
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Rev. 1.3 Aug. 2005
256MB, 512MB Unbuffered DIMMs
DDR2 SDRAM
Parameter
Symbol
DDR2-667
DDR2-533
DDR2-400
Units
Notes
min
max
min
max
min
max
DQS input low pulse width
tDQSL
0.35
x
0.35
x
0.35
x
tCK
DQS falling edge to CK setup time
tDSS
0.2
x
0.2
x
0.2
x
tCK
DQS falling edge hold time from CK
tDSH
0.2
x
0.2
x
0.2
x
tCK
Mode register set command cycle time
tMRD
2
x
2
x
2
x
tCK
Write postamble
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
19
Write preamble
tWPRE
0.35
x
0.35
x
0.35
x
tCK
Address and control input hold time
tIH
275
x375
x
475
x
ps
14,16,18
Address and control input setup time
tIS
200
x250
x
350
x
ps
14,16,18
Read preamble
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
tCK
28
Read postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
28
Active to active command period for 1KB page size products tRRD
7.5
x7.5
x
7.5
x
ns
12
Active to active command period for 2KB page size products tRRD
10
x10
x
10
x
ns
12
Four Activate Window for 1KB page size products
tFAW
37.5
ns
Four Activate Window for 2KB page size products
tFAW
50
ns
CAS to CAS command delay
tCCD
2
tCK
Write recovery time
tWR
15
x15
x
15
x
ns
Auto precharge write recovery + precharge time
tDAL
tWR+tRP
x
tWR+tRP
x
tWR+tRP
x
tCK
23
Internal write to read command delay
tWTR
7.5
x7.5
x10
x
ns
Internal read to precharge command delay
tRTP
7.5
ns
11
Exit self refresh to a non-read command
tXSNR
tRFC + 10
ns
Exit self refresh to a read command
tXSRD
200
tCK
Exit precharge power down to any non-read command
tXP
2
x
2
x
2
x
tCK
Exit active power down to read command
tXARD
2
x
2
x
2
x
tCK
9
Exit active power down to read command
(Slow exit, Lower power)
tXARDS
6 - AL
tCK
9, 10
CKE minimum pulse width
(high and low pulse width)
tCKE
3
33
tCK
ODT turn-on delay
tAOND
22222
2
tCK
ODT turn-on
tAON
tAC(min)
tAC(max)+
0.7
tAC(min)
tAC(max)+
1
tAC(min)
tAC(max)+
1
ns
13, 25
ODT turn-on(Power-Down mode)
tAONPD
tAC(min)+
2
2tCK+tAC(
max)+1
tAC(min)+
2
2tCK+tAC(
max)+1
tAC(min)+
2
2tCK+tAC
(max)+1
ns
ODT turn-off delay
tAOFD
2.5
tCK
ODT turn-off
tAOF
tAC(min)
tAC(max)+
0.6
tAC(min)
tAC(max)+
0.6
tAC(min)
tAC(max)+
0.6
ns
26
ODT turn-off (Power-Down mode)
tAOFPD
tAC(min)+
2
2.5tCK+tA
C(max)+1
tAC(min)+
2
2.5tCK+
tAC(max)+
1
tAC(min)+
2
2.5tCK+
tAC(max)+
1
ns
ODT to power down entry latency
tANPD
3
tCK
ODT power down exit latency
tAXPD
8
tCK
OCD drive mode output delay
tOIT
0
12
0
12
0
12
ns
Minimum time clocks remains ON after CKE asynchronously
drops LOW
tDelay
tIS+tCK
+tIH
tIS+tCK
+tIH
tIS+tCK
+tIH
ns
24
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| M378T3253FG0-D5 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR2 Unbuffered SDRAM MODULE |
| M378T3253FG3-CCC | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR2 Unbuffered SDRAM MODULE |
| M378T3253FG3-CD5 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR2 Unbuffered SDRAM MODULE |
| M378T3253FG3-CE6 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR2 Unbuffered SDRAM MODULE |
| M378T3253FGZ0-CE6/D5/CC | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR2 Unbuffered SDRAM MODULE |
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