TIMER A
7902 Group User’s Manual
9-31
9.5 One-shot pulse mode
9.5.3 Operation in one-shot pulse mode
When the one-shot pulse mode is selected with the operating mode select bits, the TAiOUT pin outputs
“L” level.
When the count start bit is set to “1,” the counter is enabled for counting. After that, counting starts when
a trigger is generated.
When the counter starts counting, the TAiOUT pin outputs “H” level. (When a value of “000016” is set to
the timer Ai register, the counter stops operating, the output level at pin TAiOUT remains “L,” and no timer
Ai interrupt request does not occur.)
When the counter value becomes “000016,” the output from the TAiOUT pin becomes “L” level.
Additionally, the reload register’s contents are reloaded and the counter stops counting there.
Simultaneously with , the timer Ai interrupt request bit is set to “1.”
This interrupt request bit remains set to “1” until the interrupt request is accepted or until the interrupt
request bit is cleared to “0” by software.
Figure 9.5.5 shows an example of operation in the one-shot pulse mode.
When a trigger is generated after above, the counter and TAiOUT pin perform the same operations
beginning from again. Furthermore, if a trigger is generated during counting, the counter performs
countdown once after this new trigger is generated, and then, it continues counting with the reload register’s
contents reloaded. If generating a trigger during counting, make sure that a certain time which is equivalent
to one cycle of the timer’s count source or more has passed between the previously trigger occurrence and
a new trigger occurrence.
The one-shot pulse output from the TAiOUT pin can be disabled by clearing the timer Ai mode register’s bit
2 to “0.” Accordingly, timer Ai can also be used as an internal one-shot timer that does not perform the
pulse output. In this case, the TAiOUT pin functions as a programmable I/O port pin.
In order to make the TA2OUT and TA3OUT pins serve as pulse output pins, be sure not to select the key input
interrupt pins (KI0 and KI2 pins), which are multiplexed with the above pins. (Refer to “CHAPTER 8. KEY
INPUT INTERRUPT.”)