參數(shù)資料
型號： M38001S8-XXXFS
廠商： Mitsubishi Electric Corporation
英文描述： Excalibur JFET-Input High-Output-Drive uPower Operational Amplifier 8-SOIC 0 to 70
中文描述： 8位單片機(jī)
文件頁數(shù)： 10/173頁
文件大?。?/td> 4203K
代理商： M38001S8-XXXFS
ii
3800 GROUP USER’S MANUAL
List of figures
Fig. 2.2.7 Structure of Interrupt request register 2 ................................................................... 2-9
Fig. 2.2.8 Structure of Interrupt control register 1 .................................................................. 2-10
Fig. 2.2.9 Structure of Interrupt control register 2 .................................................................. 2-10
Fig. 2.2.10 Connection of timers and setting of division ratios [Clock function] ................ 2-12
Fig. 2.2.11 Setting of related registers [Clock function] ......................................................... 2-13
Fig. 2.2.12 Control procedure [Clock function] ........................................................................ 2-14
Fig. 2.2.13 Example of a peripheral circuit .............................................................................. 2-15
Fig. 2.2.14
Connection of the timer and setting of the division ratio [Piezoelectric buzzer output]
.......... 2-15
Fig. 2.2.15 Setting of related registers [Piezoelectric buzzer output]................................... 2-16
Fig. 2.2.16 Control procedure [Piezoelectric buzzer output] .................................................. 2-16
Fig. 2.2.17 A method for judging if input pulse exists ........................................................... 2-17
Fig. 2.2.18 Setting of related registers [Measurement of frequency] ................................... 2-18
Fig. 2.2.19 Control procedure [Measurement of frequency]................................................... 2-19
Fig. 2.2.20
Connection of the timer and setting of the division ratio [Measurement of pulse width] ...........
2-20
Fig. 2.2.21 Setting of related registers [Measurement of pulse width] ................................ 2-21
Fig. 2.2.22 Control procedure [Measurement of pulse width]................................................ 2-22
Fig. 2.3.1 Memory map of serial I/O related registers ........................................................... 2-23
Fig. 2.3.2 Structure of Transmit/Receive buffer register ........................................................ 2-24
Fig. 2.3.3 Structure of Serial I/O status register .................................................................... 2-24
Fig. 2.3.4 Structure of Serial I/O control register................................................................... 2-25
Fig. 2.3.5 Structure of UART control register ......................................................................... 2-25
Fig. 2.3.6 Structure of Baud rate generator ............................................................................ 2-26
Fig. 2.3.7 Structure of Interrupt edge selection register ....................................................... 2-26
Fig. 2.3.8 Structure of Interrupt request register 1 ................................................................ 2-27
Fig. 2.3.9 Structure of Interrupt control register 1 ................................................................. 2-27
Fig. 2.3.10 Serial I/O connection examples (1) ...................................................................... 2-28
Fig. 2.3.11 Serial I/O connection examples (2) ...................................................................... 2-29
Fig. 2.3.12 Setting of Serial I/O transfer data format............................................................ 2-30
Fig. 2.3.13 Connection diagram [Communication using a clock synchronous serial I/O] 2-31
Fig. 2.3.14 Timing chart [Communication using a clock synchronous serial I/O] ............. 2-31
Fig. 2.3.15 Setting of related registers at a transmitting side
[Communication using a clock synchronous serial I/O] .................................. 2-32
Fig. 2.3.16 Setting of related registers at a receiving side
[Communication using a clock synchronous serial I/O] .................................. 2-33
Fig. 2.3.17 Control procedure at a transmitting side
[Communication using a clock synchronous serial I/O] .................................. 2-34
Fig. 2.3.18
Control procedure at a receiving side[Communication using a clock synchronous serial I/O]
. 2-35
Fig. 2.3.19 Connection diagram [Output of serial data] ......................................................... 2-36
Fig. 2.3.20 Timing chart [Output of serial data] ...................................................................... 2-36
Fig. 2.3.21 Setting of serial I/O related registers [Output of serial data]............................ 2-37
Fig. 2.3.22 Setting of serial I/O transmission data [Output of serial data].......................... 2-37
Fig. 2.3.23 Control procedure of serial I/O [Output of serial data] ...................................... 2-38
Fig. 2.3.24 Connection diagram
[Cyclic transmission or reception of block data between microcomputers] 2-39
Fig. 2.3.25
Timing chart [Cyclic transmission or reception of block data between microcomputers]........
2-40
Fig. 2.3.26 Setting of related registers
[Cyclic transmission or reception of block data between microcomputers] . 2-40
Fig. 2.3.27 Control in the master unit....................................................................................... 2-41
Fig. 2.3.28 Control in the slave unit ......................................................................................... 2-42
Fig. 2.3.29 Connection diagram [Communication using UART] ............................................ 2-43
Fig. 2.3.30 Timing chart [Communication using UART] ......................................................... 2-43
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