參數資料
型號: M38005M2-XXXSP
廠商: Mitsubishi Electric Corporation
英文描述: 4 channel 18 bit Transceiver 1 - 2.5 Gbps/Ch 289-BGA -40 to 85
中文描述: 8位單片機
文件頁數: 99/173頁
文件大小: 4203K
代理商: M38005M2-XXXSP
APPLICATION
2.4 Processor mode
2-51
3800 GROUP USER’S MANUAL
Figure 2.4.4, Figure 2.4.5 and Figure 2.4.6 show a standard timing at 8 MHz (No-Wait).
Fig. 2.4.4 Read-cycle (OE access, SRAM)
Fig. 2.4.5 Read-cycle (OE access, EPROM)
Output enabled access time of M5M5256BP
Data bus setup time before RD of 3800
td(AH—RD)
t
WL
(RD)
ta(OE)
tsu(DB—RD)
RD pulse width of 3800
RD delay time after outputting address of 3800
50 ns (max)
65 ns (min)
Address (low-order)
A
0
–A
7
(Port P0)
Address (high-order)
A
8
–A
14
(Port P1)
DQ
1
–DQ
8
(Port P2)
S
(A15)
WR
“H”
level
125 ns - 10 ns (min)
125 ns - 35 ns (min)
OE
(RD of 3800)
td(AH—RD)
t
WL
(RD)
ta(OE)
tsu(DB—RD)
:
:
:
:
RD delay time after outputting address of 3800
RD pulse width of 3800
Output enabled access time of M5M27C256AK
Data bus setup time before RD of 3800
50 ns (max)
65 ns (min)
Address (low-order)
A
0–
A
7
(Port P0)
Address (high-order)
A
8–
A
14
(Port P1)
D
0–
D
7
(Port P2)
WR
“H” level
CE
5.8 ns (max)
t
PHL
125 ns - 10ns (min)
125 ns - 35 ns (min)
OE
(RD of 3800)
td(AH—RD)
t
WL
(RD)
ta(OE)
tsu(DB—RD)
ta(OE)
tsu(DB—RD)
td(AH—RD)
t
WL
(RD)
t
PHL
:
:
:
:
:
Output delay time of 74F04
Data
Data
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