參數(shù)資料
型號： M38007E4DSP
廠商： Mitsubishi Electric Corporation
元件分類： DC/DC變換器
英文描述： 1 watt dc-dc converters
中文描述： 1瓦的DC - DC轉(zhuǎn)換器
文件頁數(shù)： 132/173頁
文件大小： 4203K
代理商： M38007E4DSP
3800 GROUP USER’S MANUAL
3-30
APPENDIX
3.5 List of registers
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O control register
0
0
0
0
0 : Transmit buffer empty
1 : Transmit shift operating
completion
0
:
Transmit disabled
1
:
Transmit enabled
0
:
Receive disabled
1
:
Receive enabled
0
:
UART
1
:
Clock synchronous serial I/O
0
:
Serial I/O disabled
(P4
4
–P4
7
:
I/O port)
1
:
Serial I/O enabled
(P4
4
–P4
7
:
Serial I/O function pin)
0 : f(X
IN
)
1 : f(X
IN
)/4
Serial I/O synchronous clock
selection bit (SCS)
At selecting clock synchronous serial I/O
0 : BRG output divided by 4
1 : External clock input
At selecting UART
0 : BRG output divided by 16
1 : External clock input divided by 16
Transmit interrupt
source selection bit
(TIC)
Transmit enable bit
(TE)
S
RDY
output enable bit
(SRDY)
0
:
I/O port (P47)
1
:
S
RDY
output pin
At reset
B
0
Name
Function
R W
1
2
3
0
0
Receive enable bit (RE)
4
5
0
0
Serial I/O enable bit
(SIOE)
Serial I/O mode
selection bit (SIOM)
6
7
BRG count source
selection bit (CSS)
Serial I/O control register (SIOCON) [Address : 1A
16
]
Fig. 3.5.5 Structure of Serial I/O control register
Fig. 3.5.6 Structure of UART control register
b7 b6 b5 b4 b3 b2 b1 b0
UART control register (UARTCON) [Address : 1B
16
]
UART control register
0
0
0
0
0
1
1
1
Character length
selection bit (CHAS)
Parity enable bit
(PARE)
Parity selection bit
(PARS)
0
:
8 bits
1
:
7 bits
0
:
Parity checking disabled
1
:
Parity checking enabled
0
:
Even parity
1
:
Odd parity
Stop bit length selection
bit (STPS)
P4
5
/TxD
P-channel
output disable bit
(POFF)
0
:
1 stop bit
1
:
2 stop bits
In output mode
0
:
CMOS output
Nothing is allocated for these bits. These are write
disabled bits. When these bits are read out, the
values are “1.”
At reset
B
0
Name
Function
R W
1
2
3
4
5
6
7
1 : N-channel open-drain
output
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