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參數(shù)資料
| 型號(hào)： | M38020M3 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | Single Output LDO, 800mA, Fixed(3.3), Internal Current limit, Thermal Overload Protection 4-SOT-223 0 to 125 |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁數(shù)： | 33/51頁 |
| 文件大?。?/td> | 692K |
| 代理商： | M38020M3 |
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MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
3802 Group
39
Serial I/O1 clock output “H” pulse width
Serial I/O2 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O2 output delay time (Note 2)
Serial I/O1 output valid time (Note 1)
Serial I/O2 output valid time (Note 2)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output rising time
Serial I/O2 clock output falling time
CMOS output rising time (Note 3)
CMOS output falling time (Note 3)
140
200
30
40
30
Symbol
Parameter
Limits
Min.
ns
Unit
SWITCHING CHARACTERISTICS 1 (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85
°C, unless otherwise noted)
tc(SCLK1)/2–30
tc(SCLK2)/2–160
tc(SCLK1)/2–30
tc(SCLK2)/2–160
–30
0
10
Typ.
Max.
twH(SCLK1)
twH(SCLK2)
twL(SCLK1)
twL(SCLK2)
td(SCLK1–TXD)
td(SCLK2–SOUT2)
tv(SCLK1–TXD)
tv(SCLK2–SOUT2)
tr(SCLK1)
tf(SCLK1)
tr(SCLK2)
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Test conditions
Fig. 36
Note1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: When the P51/SOUT2 P-channel output disable bit of the serial I/O2 control register (bit 7 of address 001D16) is “0”.
3: XOUT pin is excluded.
SWITCHING CHARACTERISTICS 2 (VCC = 3.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85
°C, unless otherwise noted)
Serial I/O1 clock output “H” pulse width
Serial I/O2 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O2 output delay time (Note 2)
Serial I/O1 output valid time (Note 1)
Serial I/O2 output valid time (Note 2)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output rising time
Serial I/O2 clock output falling time
CMOS output rising time (Note 3)
CMOS output falling time (Note 3)
350
400
50
Symbol
Parameter
Limits
Min.
ns
Unit
tc(SCLK1)/2–50
tc(SCLK2)/2–240
tc(SCLK1)/2–50
tc(SCLK2)/2–240
–30
0
20
Typ.
Max.
twH(SCLK1)
twH(SCLK2)
twL(SCLK1)
twL(SCLK2)
td(SCLK1–TXD)
td(SCLK2–SOUT2)
tv(SCLK1–TXD)
tv(SCLK2–SOUT2)
tr(SCLK1)
tf(SCLK1)
tr(SCLK2)
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Test conditions
Fig. 36
Note1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: When the P51/SOUT2 P-channel output disable bit of the serial I/O2 control register (bit 7 of address 001D16) is “0”.
3: XOUT pin is excluded.
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