3802 GROUP USER’S MANUAL
3-45
APPENDIX
3.5 List of registers
Fig. 3.5.22 Structure of Interrupt request register 1
Fig. 3.5.23 Structure of Interrupt request register 2
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
B
0
Function
At reset
R W
0
1
2
3
0
0
0
Interrupt request reigster 2 (IREQ2) [Address : 3D
16
]
Name
CNTR
0
interrupt request bit
CNTR
1
interrupt request bit
Serial I/O2 interrupt request
bit
INT
2
interrupt request bit
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
6
6
6
6
5
6
7
0
0
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “0.”
6
“0” is set by software, but not “1.”
AD conversion interrupt
request bit
INT
4
interrupt request bit
6
6
4
0
INT
3
interrupt request bit
6
0
Timer X interrupt request
bit
Serial I/O1 receive interrupt
request bit
Serial I/O1 transmit interrupt
request bit
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
B
0
Function
At reset
R W
0
1
2
3
0
0
0
Interrupt request reigster 1 (IREQ1) [Address : 3C
16
]
Name
INT
0
interrupt request bit
INT
1
interrupt request bit
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
6
6
6
6
Timer Y interrupt request bit
4
5
6
7
0
0
0
0
Timer 1 interrupt request bit
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
Timer 2 interrupt request bit
6
6
6
6
6
“0” is set by software, but not “1.”