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參數(shù)資料
| 型號(hào)： | M38025E4D768SP |
| 廠商： | Mitsubishi Electric Corporation |
| 元件分類： | DC/DC變換器 |
| 英文描述： | 1 watt dc-dc converters |
| 中文描述： | 1瓦的DC - DC轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 149/207頁(yè) |
| 文件大?。?/td> | 2389K |
| 代理商： | M38025E4D768SP |
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3802 GROUP USER’S MANUAL
3-23
APPENDIX
3.3 Notes on use
(3) Stop of data transmission and reception in a clock synchronous serial I/O mode
As for the serial I/O1 that can be used as either a clock synchronous or an asynchronous (UART) serial I/O, clear
both the transmit enable bit and receive enable bit to “0” (transmit and receive disabled) at the same time in the
following case:
G
when stopping data transmission and reception during transmitting and receiving data in the clock synchronous
mode (when data is transmitted and received in the clock synchronous serial I/O mode, any one of data
transmission and reception cannot be stopped.)
Reason
In the clock synchronous serial I/O mode, the same clock is used for transmission and reception. If any one of
transmission and reception is disabled, a bit error occurs because transmission and reception cannot be
synchronized.
In this mode, the clock circuit of the transmission circuit also operates for data reception. Accordingly, the
transmission circuit does not stop by clearing only the transmit enable bit to “0” (transmit disabled). Also, the
transmission circuit is not initialized by clearing the serial I/O1 enable bit to “0” (serial I/O1 disabled) (refer to
(1)
).
(4) The S
RDY
pin on a receiving side
When signals are output from the S
RDY
pin on the reception side by using an external clock in the clock
synchronous serial I/O mode, set all of the receive enable bit, the S
RDY
output enable bit, and the transmit enable
bit to “1” (transmit enabled).
(5) Stop of data reception in a clock synchronous
serial I/O mode
Set the serial I/O1 control register again after the
transmission and the reception circuits are reset by
clearing both the transmit enable bit and the receive
enable bit to “0.”
Clear both the transmit
enable bit (TE) and the
receive enable bit (RE) to “0”
Set the bits 0 to 3 and bit 6 of
the serial I/O1 control
register
Set both the transmit enable
bit (TE) and the receive
enable bit (RE) to “1”
Can be set with the
LDM
instruction at
the same time
(6) Control of data transmission using the transmit shift completion flag
The transmit shift completion flag changes from “1” to “0” with a delay of 0.5 to 1.5 shift clocks. When checking
the transmit shift completion flag after writing a data to the transmit buffer register for controlling a data
transmission, note this delay.
(7) Control of data transmission using an external clock
When an external clock is used as the synchronous clock for data transmission, set the transmit enable bit to “1”
at “H” level of the S
CLK
input signal. Also, write data to the transmit buffer register at “H” level of the S
CLK
input
signal.
3.3.3 Notes on the A-D converter
(1) Input of signals from signal source with high impedance to an analog input pin
Make the signal source impedance for analog input low, or equip an analog input pin with an external capacitor
of 0.01
μ
F to 1
μ
F. Further, maek sure to check the operation of application products on the user side.
Reason
The A-D converter builds in the capacitor for analog voltage comparison. Accordingly, when signals from signal
source with high impedance are input to an analog input pin, a charge and discharge noise generates. This may
cause the A-D conversion precision to be worse.
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