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參數(shù)資料
| 型號(hào)： | M38027M2D1024FS |
| 廠商： | Mitsubishi Electric Corporation |
| 元件分類： | DC/DC變換器 |
| 英文描述： | 1 watt dc-dc converters |
| 中文描述： | 1瓦的DC - DC轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 4/207頁(yè) |
| 文件大?。?/td> | 2389K |
| 代理商： | M38027M2D1024FS |
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BEFORE USING THIS USER’S MANUAL
This user’s manual consists of the following three chapters. Refer to the chapter appropriate to your conditions, such
as hardware design or software development. Chapter 3 also includes necessary information for systems development.
Be sure to refer to this chapter.
1. Organization
G
CHAPTER 1 HARDWARE
This chapter describes features of the microcomputer and operation of each peripheral function.
G
CHAPTER 2 APPLICATION
This chapter describes usage and application examples of peripheral functions, based mainly on setting examples
of related registers.
G
CHAPTER 3 APPENDIX
This chapter includes necessary information for systems development using the microcomputer, electric
characteristics, a list of registers, the masking confirmation (mask ROM version), and mark specifications which
are to be submitted when ordering.
2. Structure of register
The figure of each register structure describes its functions, contents at reset, and attributes as follows :
0 0 : SiNot available
0 : 0 page
Note 2. Bit attributesThe attributes of control register bits are classified into 3 bytes : read-only, write-only
and read and write. In the figure, these attributes are represented as follows :
: Bit in which nothing is arranged
Name
Function
At reset
R W
B
0
1
2
3
4
5
6
7
0
0
0
0
0
1
6
b0
b1
b2
b3
b4
b5
0
b6
b7
Contents immediately after reset release
Bit attributes
(Note 1)
Processor mode bits
Stack page selection bit
Nothing arranged for these bits. These are write disabled
bits. When these bits are read out, the contents are “0.”
Fix this bit to “0.”
Main clock (X
IN
-X
OUT
) stop bit
Internal system clock selection bit
b1 b0
0 : Operating
IN
-X
OUT
s selected
0 : X
CIN
-X
COUT
: Bit that is not used for control of the corresponding function
Note 1. Contents immediately after reset release
0“0” at reset release
1“1” at reset release
UndefinedUndefined or reset release
Contents determined by option at reset release
6
RRead
Read enabled
Read disabled
WWrite
Write enabled
Write disabled
(Note 2)
6
CPU mode register (CPUM) [Address : 3B
16
]
Bits
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