Addressing mode
Symbol
Function
Details
IMP
IMM
A
BIT, A
ZP
BIT, ZP
OP n
# OP n
# OP n
# OP n
# OP n
#
OP n
#
APPENDIX
3.10 Machine instructions
3-72
3802 GROUP USER'S MANUAL
Saves the contents of the accumulator in
memory at the address indicated by the stack
pointer and decrements the contents of stack
pointer by 1.
Saves the contents of the processor status
register in memory at the address indicated by
the stack pointer and decrements the contents
of the stack pointer by 1.
Increments the contents of the stack pointer
by 1 and restores the accumulator from the
memory at the address indicated by the stack
pointer.
Increments the contents of stack pointer by 1
and restores the processor status register
from the memory at the address indicated by
the stack pointer.
Shifts the contents of the memory or accumu-
lator to the left by one bit. The high order bit is
shifted into the carry flag and the carry flag is
shifted into the low order bit.
Shifts the contents of the memory or accumu-
lator to the right by one bit. The low order bit is
shifted into the carry flag and the carry flag is
shifted into the high order bit.
Rotates the contents of memory to the right by
4 bits.
Returns from an interrupt routine to the main
routine.
Returns from a subroutine to the main routine.
Subtracts the contents of memory and
complement of carry flag from the contents of
accumulator. The results are stored into the
accumulator.
Subtracts contents of complement of carry flag
and contents of the memory indicated by the
addressing mode from the memory at the ad-
dress indicated by index register X. The
results are stored into the memory of the ad-
dress indicated by index register X.
Sets the specified bit in the accumulator or
memory to “1”.
Sets the contents of the carry flag to “1”.
Sets the contents of the decimal mode flag to
“1”.
Sets the contents of the interrupt disable flag
to “1”.
Sets the contents of the index X mode flag to
“1”.
Disconnects the oscillator output from the
X
OUT
pin.
PHA
PHP
PLA
PLP
ROL
ROR
RTI
RTS
SBC
(Note 1)
(Note 5)
SEB
SEC
SED
SEI
SET
SLW
M(S)
←
A
S
←
S – 1
M(S)
←
PS
S
←
S – 1
S
←
S + 1
A
←
M(S)
S
←
S + 1
PS
←
M(S)
S
←
S + 1
PS
←
M(S)
S
←
S + 1
PC
L
←
M(S)
S
←
S + 1
PC
H
←
M(S)
S
←
S + 1
PC
L
←
M(S)
S
←
S + 1
PC
H
←
M(S)
When T = 0
A
←
A – M – C
When T = 1
M(X)
←
M(X) – M – C
Ab or Mb
←
1
C
←
1
D
←
1
I
←
1
T
←
1
E9
2A
6A
26
66
82
E5
48
08
68
28
40
60
38
F8
78
32
C2
7 0
←
←
C
←
7 0
→
→
3
3
4
4
6
6
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
1
1
0B
+
2i
5
5
8
3
2
2
2
2
0F
+
2i
2
1
5
2
7 0
C
→
→