參數(shù)資料
型號： M38039FFLSP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 16.8 MHz, MICROCONTROLLER, PDIP64
封裝： 56.40 X 17 MM, 1.78 MM PITCH, PLASTIC, SDIP-64
文件頁數(shù)： 72/119頁
文件大小： 2127K
代理商： M38039FFLSP
Rev.1.01
Jan 25, 2008
Page 56 of 117
REJ03B0212-0101
3803 Group (Spec.L)
3. SRDY3 output of reception side
Note
When signals are output from the SRDY3 pin on the reception
side by using an external clock in the clock synchronous serial
I/O mode, set all of the receive enable bit, the SRDY3 output
enable bit, and the transmit enable bit to “1” (transmit
enabled).
4. Setting serial I/O3 control register again
Note
Set the serial I/O3 control register again after the transmission
and the reception circuits are reset by clearing both the
transmit enable bit and the receive enable bit to “0”.
5.Data transmission control with referring to transmit shift
register completion flag
Note
After the transmit data is written to the transmit buffer register,
the transmit shift register completion flag changes from “1” to
“0” with a delay of 0.5 to 1.5 shift clocks. When data
transmission is controlled with referring to the flag after
writing the data to the transmit buffer register, note the delay.
6. Transmission control when external clock is selected
Note
When an external clock is used as the synchronous clock for
data transmission, set the transmit enable bit to “1” at “H” of
the SCLK3 input level. Also, write data to the transmit buffer
register at “H” of the SCLK input level.
7. Transmit interrupt request when transmit enable bit is set
Note
When using the transmit interrupt, take the following
sequence.
1. Set the serial I/O3 transmit interrupt enable bit to “0” (dis-
abled).
2. Set the transmit enable bit to “1”.
3. Set the serial I/O3 transmit interrupt request bit to “0” after
1 or more instruction has executed.
4. Set the serial I/O3 transmit interrupt enable bit to “1”
(enabled).
Reason
When the transmit enable bit is set to “1”, the transmit buffer
empty flag and the transmit shift register shift completion flag
are also set to “1”. Therefore, regardless of selecting which
timing for the generating of transmit interrupts, the interrupt
request is generated and the transmit interrupt request bit is set
at this point.
Clear both the transmit enable
bit (TE) and the receive enable
bit (RE) to “0”
Set the bits 0 to 3 and bit 6 of
the serial I/O3 control register
Set both the transmit enable bit
(TE) and the receive enable bit
(RE), or one of them to “1”
Can be set with the
LDM instruction at
the same time
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相關代理商/技術參數(shù)
參數(shù)描述
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