參數(shù)資料
型號: M38039GCH-XXXHP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 8.4 MHz, MICROCONTROLLER, PQFP64
封裝: 10 X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-64
文件頁數(shù): 8/103頁
文件大?。?/td> 1412K
代理商: M38039GCH-XXXHP
REJ03B0166-0113 Rev.1.13
Aug 21, 2009
Page 12 of 100
3803 Group (Spec.H QzROM version)
Fig 8.
Register push and pop at interrupt generation and subroutine call
Interrupt request
(Note)
M(S)
←(PCH)
(S)
←(S) 1
M(S)
←(PCL)
(
S)
(S) 1
....
.
Execute RTS
Subroutine
(S)
←(S) + 1
(PCL)
←M(S)
(S)
←(S) + 1
(PCH)
←M(S)
M(S)
←(PCH)
(S)
←(S) 1
M(S)
←(PCL)
(S)
←(S) 1
M(S)
←(PS)
(S)
←(S) 1
Interrupt
Service Routine
(S)
←(S) + 1
(PS)
←M(S)
(S)
←(S) + 1
(PCL)
←M(S)
(S)
←(S) + 1
(PCH)
←M(S)
Execute JSR
....
.
Execute RTI
Push Return Address
on Stack
Push Contents of
Processor
Status Register on Stack
I Flag is Set from
“0” to “1”
Fetch the Jump
Vector
POP Contents of
Processor Status Register
from Stack
POP Return
Address from Stack
POP Return
Address from
Stack
Push Return
Address
on Stack
Note : Condition for acceptance of an interrupt
→ Interrupt enable flag is “1”
Interrupt disable flag is “0”
On-going Routine
Table 4
Push and pop instructions of accumulator or processor status register
Push instruction to stack
Pop instruction from stack
Accumulator
PHA
PLA
Processor status register
PHP
PLP
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