參數(shù)資料
型號： M38039MFH-XXXWG
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8.4 MHz, MICROCONTROLLER, PBGA64
封裝： 6 X 6 MM, 0.65 MM PITCH, PLASTIC, FLGA-64
文件頁數(shù)： 3/119頁
文件大?。?/td> 1818K
代理商： M38039MFH-XXXWG
Rev.3.11
Apr 5, 2006
Page 98 of 113
REJ03B0017-0311
3803 Group (Spec.H)
Timing requirements and switching characteristics
Table 31
Timing requirements (1)
(Mask ROM version: VCC = 2.0 to 5.5 V, VSS = 0V, Ta = –20 to 85 °C, unless otherwise noted)
(Flash memory version: VCC = 2.7 to 5.5 V, VSS = 0V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Limits
Unit
Min.
Typ.
Max.
tW(RESET)
Reset input “L” pulse width
16
XIN cycle
tC(XIN)
Main clock XIN
input cycle time
4.5
≤ VCC ≤ 5.5 V
59.5
ns
4.0
≤ VCC < 4.5 V
10000/(86 VCC
219)
2.7
≤ VCC < 4.0 V
26
× 103/(82 VCC 3)
2.2
≤ VCC < 2.7 V
10000/(84 VCC
143)
2.0
≤ VCC < 2.2 V
10000/(105 VCC
189)
tWH(XIN)
Main clock XIN
input “H” pulse width
4.5
≤ VCC ≤ 5.5 V
25
ns
4.0
≤ VCC < 4.5 V
4000/(86 VCC
219)
2.7
≤ VCC < 4.0 V
10000/(82 VCC
3)
2.2
≤ VCC < 2.7 V
4000/(84 VCC
143)
2.0
≤ VCC < 2.2 V
4000/(105 VCC
189)
tWL(XIN)
Main clock XIN
input “L” pulse width
4.5
≤ VCC ≤ 5.5 V
25
ns
4.0
≤ VCC < 4.5 V
4000/(86 VCC
219)
2.7
≤ VCC < 4.0 V
10000/(82 VCC
3)
2.2
≤ VCC < 2.7 V
4000/(84 VCC
143)
2.0
≤ VCC < 2.2 V
4000/(105 VCC
189)
tC(XCIN)
Sub-clock XCIN input cycle time
20
s
tWH(XCIN)
Sub-clock XCIN input “H” pulse width
5
s
tWL(XCIN)
Sub-clock XCIN input “L” pulse width
5
s
tC(CNTR)
CNTR0
CNTR2
input cycle time
4.5
≤ VCC ≤ 5.5 V
120
ns
4.0
≤ VCC < 4.5 V
160
2.7
≤ VCC < 4.0 V
250
2.2
≤ VCC < 2.7 V
500
2.0
≤ VCC < 2.2 V
1000
tWH(CNTR)
CNTR0
CNTR2
input “H” pulse width
4.5
≤ VCC ≤ 5.5 V
48
ns
4.0
≤ VCC < 4.5 V
64
2.7
≤ VCC < 4.0 V
115
2.2
≤ VCC < 2.7 V
230
2.0
≤ VCC < 2.2 V
460
tWL(CNTR)
CNTR0
CNTR2
input “L” pulse width
4.5
≤ VCC ≤ 5.5 V
48
ns
4.0
≤ VCC < 4.5 V
64
2.7
≤ VCC < 4.0 V
115
2.2
≤ VCC < 2.7 V
230
2.0
≤ VCC < 2.2 V
460
tWH(INT)
INT00, INT01, INT1, INT2,
INT3, INT40, INT41
input “H” pulse width
4.5
≤ VCC ≤ 5.5 V
48
ns
4.0
≤ VCC < 4.5 V
64
2.7
≤ VCC < 4.0 V
115
2.2
≤ VCC < 2.7 V
230
2.0
≤ VCC < 2.2 V
460
tWL(INT)
INT00, INT01, INT1, INT2,
INT3, INT40, INT41
input “L” pulse width
4.5
≤ VCC ≤ 5.5 V
48
ns
4.0
≤ VCC < 4.5 V
64
2.7
≤ VCC < 4.0 V
115
2.2
≤ VCC < 2.7 V
230
2.0
≤ VCC < 2.2 V
460
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