41
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Fig. DE-2 Structure of interrupt interval determination control register
Fig. DE-3 Interrupt interval determination operation example (at rising edge active)
Interrupt interval determination circuit operating selection bit
0 : Stopped
1 : Operating
Counter sampling clock selection bit
0 : f(X
IN
)/256
1 : f(X
IN
)/512
Noise filter sampling clock selection bits(INT
2
)
0 0 : Filter stop
0 1 : f(X
IN
)/64
1 0 : f(X
IN
)/128
1 1 : f(X
IN
)/256
One-sided/both-sided edge detection selection bit
0 : One-sided edge detection
1 : Both-sided edge detection
Not used (return “0” when read)
b7
Interrupt interval determination control register
(IIDCON : address 0031
16
)
b0
Noise filter
Sampling clock
(When IIDCON
4
= “0”)
INT
2
pin
Acceptance
of interrupt
Counter
sampling clock
6
3
FF
6
3
FF
1
8-bit binary
up counter value
Interrupt interval
determination
register value
Remote control
interrupt request
Remote control
interrupt request
Counter overflow
interrupt request
Remote control
interrupt request
N
2
3
4
5
6
0
1
2
3
0
1
FE
FF
0
0
N
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