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參數(shù)資料
| 型號(hào)： | M38197MA-XXXFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 4.2 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100 |
| 文件頁數(shù)： | 57/63頁 |
| 文件大?。?/td> | 870K |
| 代理商： | M38197MA-XXXFP |
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57
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
P56/SCLK3,
P52/SCLK2,
P66/SCLK11
Serial clock output port
Note : Ports P8 and PA need external resistors.
CL
P0, P1, P20–P23,
P3, P8, P9, PA
High-breakdown-voltage
P-channel open-drain
output port
CL
(Note)
VEE
Symbol
tW(RESET)
tC(XIN)
tWH(XIN)
tWL(XIN)
tC(XcIN)
tWH(XcIN)
tWL(XcIN)
tC(CNTR)
tWH(CNTR)
tWL(CNTR)
tWH(INT)
tWL(INT)
tC(SCLK)
tWH(SCLK)
tWL(SCLK)
tsu(SCLK–SIN)
th(SCLK–SIN)
TIMING REQUIREMENTS (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –10 to 85°C, unless otherwise noted)
Parameter
Reset input “L” pulse width
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
Sub-clock input cycle time (XCIN input)
Sub-clock input “H” pulse width
Sub-clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0–INT4 input “H” pulse width
INT0–INT4 input “L” pulse width
Serial I/O clock input cycle time
Serial I/O clock input “H” pulse width
Serial I/O clock input “L” pulse width
Serial I/O input setup time
Serial I/O input hold time
Limits
Min.
2.0
119
30
20
5.0
4.0
1.6
80
1.0
400
200
Typ.
Max.
Unit
s
ns
s
ns
s
ns
SWITCHING CHARACTERISTICS (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –10 to 85°C, unless otherwise noted)
Symbol
tWH(SCLK)
tWL(SCLK)
td(SCLK–SOUT)
tv(SCLK–SOUT)
tr(SCLK)
tf(SCLK)
tr(Pch–strg)
tf(Pch–weak)
Parameter
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
Serial I/O output delay time
Serial I/O output hold time
Serial I/O clock output rising time
Serial I/O clock output falling time
High-breakdown-voltage P-channel open-
drain output rising time (Note 1)
Test conditions
CL = 100 pF
VEE = VCC –36 V
Limits
Min.
tc(SCLK)
/2–160
tc(SCLK)
/2–160
0
Typ.
55
1.8
Max.
0.2tc(SCLK)
40
Unit
ns
s
Notes 1 : When the bit 7 of the FLDC mode register 1 (address 003616) is at “0”.
2: When the bit 7 of the FLDC mode register 1 (address 003616) is at “1”.
Fig. ZA-2 Circuit for measuring output switching characteristics
High-breakdown-voltage P-channel open-
drain output falling time (Note 2)
CL = 100 pF
VEE = VCC –36 V
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