參數(shù)資料
型號(hào)： M38259EFFP
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁(yè)數(shù)： 11/71頁(yè)
文件大?。?/td> 1480K
代理商： M38259EFFP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
18
Table 8. I/O ports functions
Related SFRs
PULL register A
Segment output enable
register
PULL register A
Segment output enable
register
Port P1 output
control register
PULL register A
Interrupt control register 2
PULL register A
Segment output enable
register
Clock output control
register
PULL register A
Interrupt edge selection
register
PULL register A
Serial I/O control register
Serial I/O status register
UART control register
PULL register B
Interrupt edge selection
register
PULL register B
Timer X mode register
PULL register B
Timer X mode register
PULL register B
Timer Y mode register
PULL register B
Timer 123 mode register
PULL register B
A-D control register
PULL register B
A-D control register
PULL register B
PULL register A
CPU mode register
LCD mode register
Input/Output
Output
Input/output,
individual bits
Input/output,
individual bits
Output
Input/output,
individual bits
Input/output,
individual bits
Input/output,
individual bits
Input
Input/output,
individual bits
Input/output,
individual bits
Output
Name
Port P0
Port P1
Port P2
Port P3
Port P4
Port P5
Port P6
Port P7
Port P8
Common
Segment
Pin
P00/SEG26–
P07/SEG33
P10/SEG34–
P15/SEG39
P16 , P17
P20–P27
P30/SEG18–
P37/SEG25
P40/f(XIN)/
f(XIN)/2,
P41/f(XIN)/5/
f(XIN)/10
P42/INT0,
P43/INT1
P44/RXD
P54/TXD
P46/SCLK
P47/SRDY
P50/INT2,
P51/INT3
P52/RTP0,
P53/RTP1
P54/CNTR0
P55/CNTR1
P56/TOUT
P57/ADT
P60/AN0–
P67/AN7
P70
P71–P77
P80/XCOUT
P81/XCIN
COM0–COM3
SEG0–SEG17
Non-Port Function
LCD segment output
Key-on wake up
interrupt input
LCD segment output
Clock output
External interrupt input
Serial I/O function I/O
External interrupt input
Real time port
function output
Timer X function I/O
Timer Y function input
Timer 2 output
A-D trigger input
A-D conversion input
Sub-clock
generating circuit
I/O Format
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
LCD common output
LCD segment output
Diagram No.
(1)
(2)
(1)
(2)
(3)
(4)
(5)
(6)
(2)
(7)
(8)
(9)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
Note 1: When using double-function ports as functional I/O pins, refer the method to the relevant sections.
2: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction.
When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate.
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