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參數(shù)資料
| 型號(hào)： | M38268MCLXXXFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100 |
| 文件頁數(shù)： | 22/80頁 |
| 文件大?。?/td> | 1561K |
| 代理商： | M38268MCLXXXFP |
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3826 Group
28
Timer 1, Timer 2, Timer 3
Timer 1, timer 2, and timer 3 are 8-bit timers. The count source for
each timer can be selected by timer 123 mode register. The timer
latch value is not affected by a change of the count source. How-
ever, because changing the count source may cause an inadvert-
ent count down of the timer. Therefore, rewrite the value of timer
whenever the count source is changed.
qTimer 2 Write Control
If the timer 2 write control bit is “0”, when the value is written in the
address of timer 2, the value is loaded in the timer 2 and the latch
at the same time.
If the timer 2 write control bit is “1”, when the value is written in the
address of timer 2, the value is loaded only in the latch. The value
in the latch is loaded in timer 2 after timer 2 underflows.
qTimer 2 Output Control
When the timer 2 (TOUT) is output enabled, an inversion signal
from pin TOUT is output each time timer 2 underflows.
In this case, set the port P56 shared with the port TOUT to the out-
put mode.
sNote on Timer 1 to Timer 3
When the count source of timers 1 to 3 is changed, the timer
counting value may be changed large because a thin pulse is gen-
erated in count input of timer. If timer 1 output is selected as the
count source of timer 2 or timer 3, when timer 1 is written, the
counting value of timer 2 or timer 3 may be changed large be-
cause a thin pulse is generated in timer 1 output.
Therefore, set the value of timer in the order of timer 1, timer 2
and timer 3 after the count source selection of timer 1 to 3.
Fig. 23 Structure of timer 123 mode register
TOUT output active edge switch bit
0 : Start at “H” output
1 : Start at “L” output
TOUT/
φ output control bit
0 : TOUT/
φ output disabled
1 : TOUT/
φ output enabled
Timer 2 write control bit
0 : Write data in latch and counter
1 : Write data in latch only
Timer 2 count source selection bit
0 : Timer 1 output
1 : f(XIN)/16
(or f(XCIN)/16 in low-speed mode)
Timer 3 count source selection bit
0 : Timer 1 output
1 : f(XIN)/16
(or f(XCIN)/16 in low-speed mode)
Timer 1 count source selection bit
0 : f(XIN)/16
(or f(XCIN)/16 in low-speed mode)
1 : f(XCIN)
Not used (return “0” when read)
Timer 123 mode register
(T123M :address 002916)
Note: Internal clock
φ is f(XCIN)/2 in the low-speed mode.
b7
b0
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