參數(shù)資料
型號(hào)： M3826AEFGP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁(yè)數(shù)： 59/68頁(yè)
文件大?。?/td> 1169K
代理商： M3826AEFGP
Rev.1.00
Aug 06, 2008
page 60 of 64
REJ03B0251-0100
4286 Group
REGISTER STRUCTURE
V12
V11
V10
Timer control register V1
Auto-control output by timer 1 is invalid
Auto-control output by timer 1 is valid
Carrier wave output (CARRY)
Bit 5 of watchdog timer (WDT)
Stop (Timer 1 state retained)
Operating
0
1
0
1
0
1
Carrier wave output auto-control bit
Timer 1 count source selection bit
Timer 1 control bit
at reset : 0002
W
at RAM back-up : 0002
V23
V22
V21
V20
Timer control register V2
To expand “H” interval is invalid
To expand “H” interval is valid (when V22=1 selected)
Carrier wave generation function invalid
Carrier wave generation function valid
f(XIN)
f(XIN)/2
Stop (Timer 2 state retained)
Operating
0
1
0
1
0
1
0
1
Carrier wave “H” interval expansion bit
Carrier wave generation function control bit
Timer 2 count source selection bit
Timer 2 control bit
at reset : 00002
W
at RAM back-up : 00002
PU03
PU02
PU01
PU00
Pull-down transistor OFF, key-on wakeup invalid
Pull-down transistor ON, key-on wakeup valid
Pull-down transistor OFF, key-on wakeup invalid
Pull-down transistor ON, key-on wakeup valid
Pull-down transistor OFF, key-on wakeup invalid
Pull-down transistor ON, key-on wakeup valid
Pull-down transistor OFF, key-on wakeup invalid
Pull-down transistor ON, key-on wakeup valid
Ports G2, G3 pull-down transistor control
bit
Ports G0, G1 pull-down transistor control
bit
Port E1 pull-down transistor control bit
Port E0 pull-down transistor control bit
Pull-down control register PU0
at reset : 00002
at RAM back-up : state retained
W
0
1
0
1
0
1
0
1
PU13
PU12
PU11
PU10
Pull-down transistor OFF, key-on wakeup invalid
Pull-down transistor ON, key-on wakeup valid
Pull-down transistor OFF, key-on wakeup invalid
Pull-down transistor ON, key-on wakeup valid
Pull-down transistor OFF, key-on wakeup invalid
Pull-down transistor ON, key-on wakeup valid
Pull-down transistor OFF, key-on wakeup invalid
Pull-down transistor ON, key-on wakeup valid
Port D7 pull-down transistor control bit
Port D6 pull-down transistor control bit
Port D5 pull-down transistor control bit
Port D4 pull-down transistor control bit
Pull-down control register PU1
at reset : 00002
at RAM back-up : state retained
W
0
1
0
1
0
1
0
1
Note: “W” represents write enabled.
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