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參數(shù)資料
| 型號： | M38270M3MXXXGP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | Single Micropower Rail-To-Rail Input/Output Op Amp 5-SOT-23 -40 to 125 |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數(shù)： | 33/70頁 |
| 文件大?。?/td> | 1112K |
| 代理商： | M38270M3MXXXGP |
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33
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3827 Group
A-D CONVERTER
[A-D Conversion Register (AD)] 0035
16
The A-D conversion register is a read-only register that contains
the result of an A-D conversion. During A-D conversion, do not
read this register.
[A-D Control Register (ADCON)] 0034
16
The A-D control register controls the A-D conversion process. Bits
0 to 2 are analog input pin selection bits. Bit 3 is an A-D conver-
sion completion bit and “0” during A-D conversion, then changes
to “1” when the A-D conversion is completed. Writing “0” to this bit
starts the A-D conversion. Bit 4 controls the transistor which
breaks the through current of the resistor ladder. When bit 5, which
is the AD external trigger valid bit, is set to “1”, A-D conversion is
started even by a rising edge or falling edge of an ADT input. Set
ports which share with ADT pins to input when using an A-D exter-
nal trigger.
[Comparison Voltage Generator]
The comparison voltage generator divides the voltage between
AV
SS
and V
REF
, and outputs the divided voltages.
[Channel Selector]
The channel selector selects one of the input ports P6
7
/AN
7
–P6
0
/
AN
0,
and inputs it to the comparator.
[Comparator and Control Circuit]
The comparator and control circuit compares an analog input volt-
age with the comparison voltage and stores the result in the A-D
conversion register. When an A-D conversion is completed, the
control circuit sets the AD conversion completion bit and the AD
interrupt request bit to “1”.
Note that the comparator is constructed linked to a capacitor, so
set f(X
IN
) to at least 500 kHz during A-D conversion.
Use a clock divided the main clock X
IN
as the internal clock
φ
.
Fig. 34 A-D converter block diagram
Fig. 33 Structure of A-D control register
A-D control register
(ADCON : address 0031
16
)
Analog input pin selection bits
0 0 0 : P6
0
/S
IN2
/AN
0
0 0 1 : P6
1
/S
OUT2
/AN
1
0 1 0 : P6
2
/S
CLK21
/AN
2
0 1 1 : P6
3
/S
CLK22
/AN
3
1 0 0 : P6
4
/AN
4
1 0 1 : P6
5
/AN
5
1 1 0 : P6
6
/AN
6
1 1 1 : P6
7
/AN
7
AD conversion completion bit
0 : Conversion in progress
1 : Conversion completed
V
REF
input switch bit
0 : OFF
1 : ON
AD external trigger valid bit
0 : A-D external trigger invalid
1 : A-D external trigger valid
Interrupt source selection bit
0 : Interrupt request at A-D
conversion completed
1 : Interrupt request at ADT
input rising or falling
Reference voltage input selection bit
0 : V
REF
1 : P5
6
/DA
1
b7
b0
b7 b0
b9 b8 b7 b6 b5 b4 b3 b2
b7 b0
b9 b8
b7 b0
b7 b6 b5 b4 b3 b2
8-bit read (Read only address 0032
16
.)
(Address 0032
16
)
10-bit read (Read address 0033
16
first.)
(Address 0033
16
)
(Address 0032
16
)
Note:
High-order 6 bits of address 0033
16
becomes “0” at reading.
b1 b0
Data bus
A-D control register
A-D conversion register
Resistor ladder
AV
SS
Comparater
ADT/A-D interrupt request
b7
b0
A-D control register
3
P6
0
/S
IN2
/AN
0
P6
1
/S
OUT2
/AN
1
P6
2
/S
CLK21
/AN
2
P6
3
/S
CLK22
/AN
3
P6
4
/AN
4
P6
5
/AN
5
P6
6
/AN
6
P6
7
/AN
7
10
P4
0
/ADT
V
REF
A-D conversion register
(H)
(L)
P5
6
/DA
1
C
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