參數(shù)資料
型號(hào)： M38271E9MXXXHP
廠商： Mitsubishi Electric Corporation
英文描述： Quad Micropower Rail-To-Rail Input/Output Op Amp 14-PDIP -40 to 125
中文描述： 單芯片8位CMOS微機(jī)
文件頁(yè)數(shù)： 42/70頁(yè)
文件大?。?/td> 1112K
代理商： M38271E9MXXXHP
42
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
3827 Group
MITSUBISHI MICROCOMPUTERS
T
OUT
/
φ
CLOCK OUTPUT FUNCTION
The internal system clock
φ
or timer 2 divided by 2 (T
OUT
output)
can be output from port P4
3
by setting the T
OUT
/
φ
output control
bit (bit 1) of the timer 123 mode register and the T
OUT
/
φ
output
control register. Set bit 3 of the port P4 direction register to “1”
when outputting the clock.
Fig. 47 Structure of T
OUT
/
φ
output-related register
T
OUT
/
φ
output control bit
0 :
φ
clock output
1 : T
OUT
output
Not used (return “0” when read)
T
OUT
/
φ
output control register
(CKOUT : address 002A
16
)
b7
b0
Timer 123 mode register
(T123M : address 0029
16
)
T
OUT
output active edge switch bit
0 : Start on “H” output
1 : Start on “L” output
T
OUT
/
φ
output control bit
0 : T
OUT
/
φ
output disable
1 : T
OUT
/
φ
output enable
Timer 2 write control bit
0 : Write data in latch and timer
1 : Write data in latch only
Timer 2 count source selection bit
0 : Timer 1 output
1 : f(X
IN
)/16
(or f(X
CIN
)/16 in low-speed mode
8
)
Timer 3 count source selection bit
0 : Timer 1 output
1 : f(X
IN
)/16
(or f(X
CIN
)/16 in low-speed mode
8
)
Timer 1 count source selection bit
0 : f(X
IN
)/16
(or f(X
CIN
)/16 in low-speed mode
8
)
1 : f(X
CIN
)
Not used (return “0” when read)
8
: Internal clock
φ
is f(X
CIN
)/2 in low-speed mode.
b7
b0
相關(guān)PDF資料
PDF描述
M38271EA-XXXFP Quad Micropower Rail-To-Rail Input/Output Op Amp 14-PDIP -40 to 125
M38271EA-XXXFS Quad Micropower Rail-To-Rail Input/Output Op Amp 14-TSSOP
M38271EA-XXXGP Quad Micropower Rail-To-Rail Input/Output Op Amp 14-TSSOP
M38271EA-XXXHP Quad Micropower Rail-To-Rail Input/Output Op Amp 14-TSSOP -40 to 125
M38271EAMXXXFP Quad Micropower Rail-To-Rail Input/Output Op Amp 14-TSSOP -40 to 125
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