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參數資料
| 型號： | M38271EB-XXXGP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數： | 18/70頁 |
| 文件大?。?/td> | 1112K |
| 代理商： | M38271EB-XXXGP |
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18
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
3827 Group
MITSUBISHI MICROCOMPUTERS
INTERRUPTS
Interrupts occur by seventeen sources: seven external, nine inter-
nal, and one software.
Interrupt Control
Each interrupt except the BRK instruction interrupt have both an
interrupt request bit and an interrupt enable bit, and is controlled
by the interrupt disable flag. An interrupt occurs if the correspond-
ing interrupt request and enable bits are “1” and the interrupt
disable flag is “0.” Interrupt enable bits can be set or cleared by
software. Interrupt request bits can be cleared by software, but
cannot be set by software. The BRK instruction interrupt and reset
cannot be disabled with any flag or bit. The I flag disables all inter-
rupts except the BRK instruction interrupt and reset. If several
interrupts requests occurs at the same time the interrupt with high-
est priority is accepted first.
Interrupt Operation
Upon acceptance of an interrupt the following operations are auto-
matically performed:
1. The contents of the program counter and processor status
register are automatically pushed onto the stack.
2. The interrupt disable flag is set and the corresponding
interrupt request bit is cleared.
3. The interrupt jump destination address is read from the vec-
tor table into the program counter.
I
Notes
When the active edge of an external interrupt (INT
0
–INT
2
, CNTR
0
,
CNTR
1
) is set or when switching interrupt sources of ADT/A-D
conversion interrupt, the corresponding interrupt request bit may
also be set. Therefore, take following sequence:
(1) Disable the external interrupt which is selected.
(2) Change the active edge in interrupt edge selection register
(timer XY mode register when using CNTR
0
, CNTR
1
)
(3) Clear the set interrupt request bit to “0.”
(4) Enable the external interrupt which is selected.
Notes1:
Vector addresses contain interrupt jump destination addresses.
2:
Reset function in the same way as an interrupt with the highest priority.
Table 6 Interrupt vector addresses and priority
Remarks
Interrupt Request
Generating Conditions
At reset
At detection of either rising or
falling edge of INT
0
input
At detection of either rising or
falling edge of INT
1
input
At completion of serial I/O1 data
reception
At completion of serial I/O1
transmit shift or when transmis-
sion buffer is empty
At timer X underflow
At timer Y underflow
At timer 2 underflow
At timer 3 underflow
At detection of either rising or
falling edge of CNTR
0
input
At detection of either rising or
falling edge of CNTR
1
input
At timer 1 underflow
At detection of either rising or
falling edge of INT
2
input
At completion of serial I/O2 data
transmission or reception
At falling of conjunction of input
level for port P2 (at input mode)
At falling of ADT input
Interrupt Source
Low
FFFC
16
FFFA
16
High
FFFD
16
FFFB
16
Priority
Vector Addresses
(Note 1)
Reset
(Note 2)
INT
0
INT
1
Serial I/O1
reception
Serial I/O1
transmission
Timer X
Timer Y
Timer 2
Timer 3
CNTR
0
CNTR
1
Timer 1
INT
2
Serial I/O2
Key input
(Key-on wake-up)
ADT
A-D conversion
BRK instruction
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
FFF9
16
FFF7
16
FFF5
16
FFF3
16
FFF1
16
FFEF
16
FFED
16
FFEB
16
FFE9
16
FFE7
16
FFE5
16
FFE3
16
FFE1
16
FFDF
16
FFDD
16
FFF8
16
FFF6
16
FFF4
16
FFF2
16
FFF0
16
FFEE
16
FFEC
16
FFEA
16
FFE8
16
FFE6
16
FFE4
16
FFE2
16
FFE0
16
FFDE
16
FFDC
16
At completion of A-D conversion
At BRK instruction execution
Non-maskable
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Valid when serial I/O1 is selected
Valid when serial I/O1 is selected
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Valid when serial I/O2 is selected
External interrupt
(valid when an “L” level is applied)
Valid when ADT interrupt is se-
lected External interrupt
(Valid at falling)
Valid when A-D interrupt is se-
lected
Non-maskable software interrupt
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