參數(shù)資料
型號(hào)： M38271EE-XXXFS
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁(yè)數(shù)： 41/70頁(yè)
文件大?。?/td> 1112K
代理商： M38271EE-XXXFS
41
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3827 Group
WATCHDOG TIMER
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example, be-
cause of a software runaway).
The watchdog timer consists of an 8-bit watchdog timer L and a 6-
bit watchdog timer H. At reset or writing to the watchdog timer
control register (address 0037
16
), the watchdog timer is set to
“3FFF
16
.” When any data is not written to the watchdog timer con-
trol register (address 0037
16
) after reset, the watchdog timer is in
stop state. The watchdog timer starts to count down from “3FFF
16
”
by writing an optional value into the watchdog timer control regis-
ter (address 0037
16
) and an internal reset occurs at an underflow.
Accordingly, programming is usually performed so that writing to
the watchdog timer control register (address 0037
16
) may be
started before an underflow. The watchdog timer does not function
when an optional value have not written to the watchdog timer
control register (address 0037
16
). When address 0037
16
is read,
the following values are read:
G
value of high-order 6-bit counter
G
value of STP instruction disable bit
G
value of count source selection bit.
When bit 6 of the watchdog timer control register (address 0037
16
)
is set to “0,” the STP instruction is valid. The STP instruction is dis-
abled by rewriting this bit to “1.” At this time, if the STP instruction
is executed, it is processed as an undefined instruction, so that a
reset occurs inside.
This bit cannot be rewritten to “0” by programming. This bit is “0”
immediately after reset.
The count source of the watchdog timer becomes the system
clock
φ
divided by 8. The detection time in this case is set to 8.19 s
at X
CIN
= 32 kHz and 65.536 ms at X
IN
= 4 MHz.
However, count source of high-order 6-bit timer can be connected
to a signal divided system clock by 8 directly by writing the bit 7 of
the watchdog timer control register (address 0037
16
) to “1.” The
detection time in this case is set to 32 ms at X
CIN
= 32 kHz and
256
μ
s at X
IN
= 4 MHz. There is no difference in the detection time
between the middle-speed mode and the high-speed mode.
Fig. 44 Block diagram of watchdog timer
Fig. 45 Structure of watchdog timer control register
Fig. 46 Timing of reset output
X
IN
Data bus
X
CIN
“1”
“0”
Internal
system clock
selection bit
“0”
“1”
1/16
Watchdog timer
H (6)
Watchdog timer count
source selection bit
Reset circuit
Undefined instruction
Reset
“3F
16
” is set when
watchdog timer is
written to.
Internal reset
RESET
IN
Reset release time wait
Watchdog timer
L (8)
“FF
16
” is set when
watchdog timer is
written to.
STP instruction
STP instruction disable bit
Watchdog timer H (for read-out of high-order 6 bit)
“3FFF
16
” is set to the watchdog timer by writing values to this address.
Watchdog timer H count source selection bit
0 : Internal system clock/2048 (f(X
IN
)/4096)
1 : Internal system clock/8 (f(X
IN
)/16)
STP instruction disable bit
0 STP instruction enabled
1 : STP instruction disabled
b7
Watchdog timer register (address 0037
16
)
WDTCON
b0
Internal
reset signal
Watchdog timer detection
2
ms
(f(X
IN
) = 4MH
Z
)
f(X
IN)
相關(guān)PDF資料
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