參數(shù)資料
型號(hào)： M38272MEMXXXGP
廠商： Mitsubishi Electric Corporation
英文描述： Dual Low-Power, Rail-to-Rail Input/Output Operational Amplifier 20-LCCC -55 to 125
中文描述： 單芯片8位CMOS微機(jī)
文件頁(yè)數(shù)： 21/70頁(yè)
文件大小： 1112K
代理商： M38272MEMXXXGP
21
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3827 Group
CNTR
active
edge switch bit
Timer 1 count source
selection bit
Real time port
control bit “0”
“1”
P5
5
/CNTR
1
“0”
f(X
IN
)/16
(f(X
CIN
)
16 in
φ
= X
CIN
divided by 2)
1
active
CNTR
“10”
Timer Y stop
control bit
Timer Y (low) latch (8)
Falling edge detection
Period
Timer Y
interrupt
request
Pulse width HL continuously measurement mode
Rising edge detection
“00”,“01”,“11”
Timer Y operating
mode bit
Timer X
interrupt
request
Timer X mode register
write signal
P5
4
/CNTR
0
Q
Q
T
S
P5
4
direction register
Pulse output mode
P5
4
latch
Timer X stop
control bit
“0”
“1”
Timer X write
control bit
Q D
Latch
Q D
Latch
“1”
“0”
“1”
“10”
Timer X operat-
ing mode bits
“00”,“01”,“11”
f(X
IN
)/16
(f(X
IN
)/16 in low-speed mode
8
)
Pulse width
measurement
mode
CNTR
0
active
edge switch bit
Pulse output mode
Q
Q
T
S
“0”
P4
3
direction register
P4
3
latch
“1”
T
output
active edge
switch bit
Timer 2 write
control bit
“0”
“1”
T
output
control bit
“1”
P4
3
/
φ
/T
OUT
X
CIN
Tim“1”
source selection bit
“0”
Timer 2
interrupt
request
Timer 3
interrupt
request
Timer 2 count source
selection bit
Timer 1
interrupt
request
Data bus
f(X
IN
)/16
(f(X
CIN
)/16 in
φ
= X
CIN
divided by 2)
f(X
IN
)/16
(f(X
CIN
)
16 in
φ
=X
CIN
divided by 2)
f(X
IN
)/16(f(X
CIN
)/16 in low-speed mode
8
)
CNTR
0
interrupt
request
CNTR
1
interrupt
request
Timer Y operating mode bit
“00”,“01”,“10”
“11”
Real time port
control bit “1”
P5
latch
Real time port
control bit “1”
P5
3
latch
Timer Y (low) (8)
Timer Y (high) (8)
Timer 3 latch (8)
Timer 3 (8)
Timer 1 latch (8)
Timer 1 (8)
Timer 2 latch (8)
Timer 2 (8)
Timer X (low) (8)
Timer X (high) (8)
Timer X (low) latch (8)
Timer X (high) latch (8)
Timer Y (high) latch (8)
T
output
control bit
“0”
“0”
“0”
P5
2
P5
3
P5
2
direction register
P5
3
direction register
P5
2
data for real time port
P5
3
data for real time port
TIMERS
The 3827 group has five timers: timer X, timer Y, timer 1, timer 2,
and timer 3. Timer X and timer Y are 16-bit timers, and timer 1,
timer 2, and timer 3 are 8-bit timers.
All timers are down count timers. When the timer reaches “00
16
”,
an underflow occurs at the next count pulse and the correspond-
ing timer latch is reloaded into the timer and the count is
continued. When a timer underflows, the interrupt request bit cor-
responding to that timer is set to “1”.
Read and write operation on 16-bit timer must be performed for
both high and low-order bytes. When reading a 16-bit timer, read
the high-order byte first. When writing to a 16-bit timer, write the
low-order byte first. The 16-bit timer cannot perform the correct op-
eration when reading during the write operation, or when writing
during the read operation.
Fig. 17 Timer block diagram
相關(guān)PDF資料
PDF描述
M38272MEMXXXHP Dual Low-Power, Rail-to-Rail Input/Output Operational Amplifier 10-CFP -55 to 125
M38272MFMXXXHP Dual Low-Power, Rail-to-Rail Input/Output Operational Amplifier 8-CDIP -55 to 125
M38273E4MXXXFP Dual Low-Power, Rail-to-Rail Input/Output Operational Amplifier 20-LCCC -55 to 125
M38273E4MXXXFS Dual Low-Power, Rail-to-Rail Input/Output Operational Amplifier 8-CDIP -55 to 125
M38273E4MXXXGP Dual Low-Power, Rail-to-Rail Input/Output Operational Amplifier 8-CDIP -55 to 125
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