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參數(shù)資料
| 型號： | M38274E7MXXXFP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁數(shù)： | 35/70頁 |
| 文件大小： | 1112K |
| 代理商： | M38274E7MXXXFP |
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35
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3827 Group
LCD DRIVE CONTROL CIRCUIT
The 3827 group has the built-in Liquid Crystal Display (LCD) drive
control circuit consisting of the following.
G
LCD display RAM
G
Segment output enable register
G
LCD mode register
G
Voltage multiplier
G
Selector
G
Timing controller
G
Common driver
G
Segment driver
G
Bias control circuit
A maximum of 40 segment output pins and 4 common output pins
can be used.
Fig. 38 Structure of LCD mode register
Up to 160 pixels can be controlled for LCD display. When the LCD
enable bit is set to “1” after data is set in the LCD mode register,
the segment output enable register and the LCD display RAM, the
LCD drive control circuit starts reading the display data automati-
cally, performs the bias control and the duty ratio control, and
displays the data on the LCD panel.
Table 7 Maximum number of display pixels at each duty ratio
Duty ratio
Maximum number of display pixel
80 dots
or 8 segment LCD 10 digits
120 dots
or 8 segment LCD 15 digits
160 dots
or 8 segment LCD 20 digits
2
3
4
Segment output enable bit 0
0 : Output ports P3
0
–P3
5
1 : Segment output SEG
18
–SEG
23
Segment output enable bit 1
0 : Output ports P3
6
, P3
7
1 : Segment output SEG
24
,SEG
25
Segment output enable bit 2
0 : I/O ports P0
0
–P0
5
1 : Segment output SEG
26
–SEG
31
Segment output enable bit 3
0 : I/O ports P0
6
,P0
7
1 : Segment output SEG
32
,SEG
33
Segment output enable bit 4
0 : I/O port P1
0
1 : Segment output SEG
34
Segment output enable bit 5
0 : I/O ports P1
1
–P1
5
1 : Segment output SEG
35
–SEG
39
LCD output enable bit
0 : Disable
1 : Enable
Not used (return “0” when read)
(Do not write “1” to this bit)
Segment output enable register
(SEG : address 0038
16
)
b7
b0
LCD mode register
(LM : address 0039
16
)
Duty ratio selection bits
0 0 : Not used
0 1 : 2 duty (use COM
0
, COM
1
)
1 0 : 3 duty (use COM
0
–COM
2
)
1 1 : 4 duty (use COM
0
–COM
3
)
Bias control bit
0 : 1/3 bias
1 : 1/2 bias
LCD enable bit
0 : LCD OFF
1 : LCD ON
Voltage multiplier control bit
0 : Voltage multiplier disabled
1 : Voltage multiplier enabled
LCD circuit divider division ratio selection bits
0 0 : 1 division of clock input
0 1 : 2 division of clock input
1 0 : 4 division of clock input
1 1 : 8 division of clock input
LCDCK count source selection bit (Note)
0 : f(X
CIN
)/32
1 : f(X
IN
)/8192 (f(X
CIN
)/8192 in low-speed mode)
Note :
LCDCK is a clock for a LCD timing controller.
b7
b0
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