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參數(shù)資料
| 型號(hào)： | M38275E4MXXXHP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | Dual Low-Power Rail-to-Rail Input/Output Op Amp 8-MSOP-PowerPAD -40 to 125 |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁數(shù)： | 31/70頁 |
| 文件大?。?/td> | 1112K |
| 代理商： | M38275E4MXXXHP |
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31
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3827 Group
PULSE WIDTH MODULATION (PWM)
The 3827 group has a PWM function with an 8-bit resolution,
based on a signal that is the clock input X
IN
or that clock input di-
vided by 2.
Data Setting
The PWM output pin also functions as ports P5
0
and P5
1
. Set the
PWM period by the PWM prescaler, and set the period during
which the output pulse is an “H” by the PWM register.
If PWM count source is f(X
IN
) and the value in the PWM prescaler
is n and the value in the PWM register is m (where n = 0 to 255
and m = 0 to 255) :
PWM period = 255
(n+1)/f(X
IN
)
= 51
(n+1)
μ
s (when X
IN
= 5 MHz)
Output pulse “H” period = PWM period
m/255
= 0.2
(n+1)
m
μ
s
(when X
IN
= 5 MHz)
PWM Operation
When at least either bit 1 (PWM
0
output enable bit) or bit 2 (PWM
1
output enable bit) of the PWM control register is set to “1”, opera-
tion starts by initializing the PWM output circuit, and pulses are
output starting at an “H”. When one PWM output is enabled and
that the other PWM output is enabled, PWM output which is en-
abled to output later starts pulse output from halfway.
When the PWM register or PWM prescaler is updated during
PWM output, the pulses will change in the cycle after the one in
which the change was made.
Fig. 29 Timing of PWM cycle
Fig. 30 Block diagram of PWM function
51
m
(n+1)
255
μ
s
T = [51
(n+1)]
μ
s
PWM output
m: Contents of PWM register
n : Contents of PWM prescaler
T : PWM cycle (when f(X
IN
) = 5 MHz)
Data bus
Count source
selection bit
“0”
“1”
PWM
prescaler pre-latch
PWM
register pre-latch
PWM
prescaler latch
PWM
register latch
Transfer control circuit
PWM circuit
1/2
X
IN
PWM
0
enable bit
Port P5
6
PWM prescaler
PWM
1
enable bit
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