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參數(shù)資料
| 型號： | M38275M1-XXXGP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | Dual Low-Power Rail-to-Rail Input/Output Op Amp w/Shutdown 14-PDIP -40 to 125 |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁數(shù)： | 45/70頁 |
| 文件大?。?/td> | 1112K |
| 代理商： | M38275M1-XXXGP |
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45
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3827 Group
CLOCK GENERATING CIRCUIT
The 3827 group has two built-in oscillation circuits. An oscillation
circuit can be formed by connecting a resonator between X
IN
and
X
OUT
(X
CIN
and X
COUT
). Use the circuit constants in accordance
with the resonator manufacturer's recommended values. No exter-
nal resistor is needed between X
IN
and X
OUT
since a feed-back
resistor exists on-chip. However, an external feed-back resistor is
needed between X
CIN
and X
COUT
.
To supply a clock signal externally, input it to the X
IN
pin and make
the X
OUT
pin open. The sub-clock X
CIN
-X
COUT
oscillation circuit
cannot directly input clocks that are externally generated. Accord-
ingly, be sure to cause an external resonator to oscillate.
Immediately after poweron, only the X
IN
oscillation circuit starts
oscillating, and X
CIN
and X
COUT
pins go to high impedance state.
Frequency Control
(1) Middle-speed Mode
The internal clock
φ
is the frequency of X
IN
divided by 8.
After reset, this mode is selected.
(2) High-speed Mode
The internal clock
φ
is half the frequency of X
IN
.
(3) Low-speed Mode
G
The internal clock
φ
is half the frequency of X
CIN
.
G
A low-power consumption operation can be realized by stopping
the main clock X
IN
in this mode. To stop the main clock, set bit 5
of the CPU mode register to “1”.
When the main clock X
IN
is restarted, set enough time for oscil-
lation to stabilize by programming.
Note:
If you switch the mode between middle/high-speed and low-
speed, stabilize both X
IN
and X
CIN
oscillations. The
sufficient time is required for the sub-clock to stabilize, es-
pecially immediately after poweron and at returning from
stop mode. When switching the mode between middle/high-
speed and low-speed, set the frequency on condition that
f(X
IN
)>3f(X
CIN
).
Fig. 51 Ceramic resonator circuit
Fig. 52 External clock input circuit
Oscillation Control
(1) Stop Mode
If the STP instruction is executed, the internal clock
φ
stops at an
“H” level, and X
IN
and X
CIN
oscillators stop. The value set to the
timer latch 1 and the timer latch 2 is loaded automatically to the
timer 1 and the timer 2. Thus, a value generated time for stabiliz-
ing oscillation should be set to the timer 1 latch and the timer 2
latch (low-order 8 bits for the timer 1, high-order 8 bits for the timer
2) before executing the STP instruction.
Either X
IN
or X
CIN
divided by 16 is input to timer 1 as count
source, and the output of timer 1 is connected to timer 2. The bits
of the timer 123 mode register except bit 4 are cleared to “0,” Set
the timer 1 and timer 2 interrupt enable bits to disabled (“0”) before
executing the STP instruction. Oscillator restarts at reset or when
an external interrupt is received, but the internal clock
φ
is not sup-
plied to the CPU until timer 2 underflows..This allows timer for the
clock circuit oscillation to stabilize.
(2) Wait Mode
If the WIT instruction is executed, the internal clock
φ
stops at an
“H” level. The states of X
IN
and X
CIN
are the same as the state be-
fore the executing the WIT instruction. The internal clock restarts
at reset or when an interrupt is received. Since the oscillator does
not stop, normal operation can be started immediately after the
clock is restarted.
X
CIN
X
COUT
X
IN
X
OUT
C
IN
C
OUT
C
CIN
C
COUT
Rf
Rd
X
IN
X
OUT
External oscillation
circuit
Open
V
CC
V
SS
C
CIN
C
COUT
Rf
Rd
X
CIN
X
COUT
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| M38275M1-XXXHP | Dual Low-Power Rail-to-Rail Input/Output Op Amp w/Shutdown 14-PDIP -40 to 125 |
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| M38275M1MXXXGP | Quad Low-Power Rail-to-Rail Input/Output Op Amp 14-SOIC 0 to 70 |
| M38275M1MXXXHP | Quad Low-Power Rail-to-Rail Input/Output Op Amp 14-SOIC 0 to 70 |
| M38275M2-XXXFP | Quad Low-Power Rail-to-Rail Input/Output Op Amp 14-SOIC 0 to 70 |
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