參數(shù)資料
型號： M38279EFFS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, UVPROM, 4 MHz, MICROCONTROLLER, CQCC100
封裝： WINDOWED, CERAMIC, LCC-100
文件頁數(shù)： 29/70頁
文件大?。?/td> 1112K
代理商： M38279EFFS
35
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3827 Group
LCD DRIVE CONTROL CIRCUIT
The 3827 group has the built-in Liquid Crystal Display (LCD) drive
control circuit consisting of the following.
qLCD display RAM
qSegment output enable register
qLCD mode register
qVoltage multiplier
qSelector
qTiming controller
qCommon driver
qSegment driver
qBias control circuit
A maximum of 40 segment output pins and 4 common output pins
can be used.
Fig. 38 Structure of LCD mode register
Up to 160 pixels can be controlled for LCD display. When the LCD
enable bit is set to “1” after data is set in the LCD mode register,
the segment output enable register and the LCD display RAM, the
LCD drive control circuit starts reading the display data automati-
cally, performs the bias control and the duty ratio control, and
displays the data on the LCD panel.
Table 7 Maximum number of display pixels at each duty ratio
Duty ratio
Maximum number of display pixel
80 dots
or 8 segment LCD 10 digits
120 dots
or 8 segment LCD 15 digits
160 dots
or 8 segment LCD 20 digits
2
3
4
Segment output enable bit 0
0 : Output ports P30–P35
1 : Segment output SEG18–SEG23
Segment output enable bit 1
0 : Output ports P36, P37
1 : Segment output SEG24,SEG25
Segment output enable bit 2
0 : I/O ports P00–P05
1 : Segment output SEG26–SEG31
Segment output enable bit 3
0 : I/O ports P06,P07
1 : Segment output SEG32,SEG33
Segment output enable bit 4
0 : I/O port P10
1 : Segment output SEG34
Segment output enable bit 5
0 : I/O ports P11–P15
1 : Segment output SEG35–SEG39
LCD output enable bit
0 : Disable
1 : Enable
Not used (return “0” when read)
(Do not write “1” to this bit)
Segment output enable register
(SEG : address 003816)
b7
b0
LCD mode register
(LM : address 003916)
Duty ratio selection bits
0 0 : Not used
0 1 : 2 duty (use COM0, COM1)
1 0 : 3 duty (use COM0–COM2)
1 1 : 4 duty (use COM0–COM3)
Bias control bit
0 : 1/3 bias
1 : 1/2 bias
LCD enable bit
0 : LCD OFF
1 : LCD ON
Voltage multiplier control bit
0 : Voltage multiplier disabled
1 : Voltage multiplier enabled
LCD circuit divider division ratio selection bits
0 0 : 1 division of clock input
0 1 : 2 division of clock input
1 0 : 4 division of clock input
1 1 : 8 division of clock input
LCDCK count source selection bit (Note)
0 : f(XCIN)/32
1 : f(XIN)/8192 (f(XCIN)/8192 in low-speed mode)
Note : LCDCK is a clock for a LCD timing controller.
b7
b0
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