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參數(shù)資料
| 型號： | M38503M2H-XXXFP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數(shù)： | 18/99頁 |
| 文件大?。?/td> | 1384K |
| 代理商： | M38503M2H-XXXFP |
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18
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. A)
I/O PORTS
The I/O ports have direction registers which determine the input/
output direction of each individual pin. Each bit in a direction
register corresponds to one pin, and each pin can be set to be
input port or output port.
When
“
0
”
is written to the bit corresponding to a pin, that pin
becomes an input pin. When
“
1
”
is written to that bit, that pin
becomes an output pin.
If data is read from a pin which is set to output, the value of the
port output latch is read, not the value of the pin itself. Pins set to
input are floating. If a pin set to input is written to, only the port
output latch is written to and the pin remains floating.
Pin
Name
Input/Output
I/O Structure
Non-Port Function
Table 9 I/O port function (spec. A)
Related SFRs
Port P0
Port P1
Port P2
P0
0
/S
IN2
P0
1
/S
OUT2
P0
2
/S
CLK2
P0
3
/S
RDY2
P0
4
/AN
5
–
P0
7
AN
8
P1
0
–
P1
7
P2
0
/X
COUT
P2
1
/X
CIN
P2
2
P2
3
P2
4
/RxD
P2
5
/TxD
P2
6
/S
CLK
P2
7
/CNTR
0
/S
RDY1
P3
0
/AN
0
–
P3
4
/AN
4
P4
0
/CNTR
1
P4
1
/INT
0
P4
2
/INT
1
P4
3
/INT
2
/S
CMP2
P4
4
/INT
3
/PWM
CMOS compatible
input level
CMOS 3-state output
Serial I/O2 control register
CMOS compatible
input level
CMOS 3-state output
Input/output,
individual
bits
Ref.No.
(1)
(2)
(3)
(4)
CMOS compatible
input level
N-channel open-drain
output
Port P3
Port P4
(Note)
Note:
When bits 5 to 7 of Ports P3 and P4 are read out, the contents are undefined.
By setting the port P0, P1, P2 pull-up control register (address
0012
16
), the port P3 pull-up control register (address 0013
16
), or
the port P4 pull-up control register (address 0014
16
), ports can
control pull-up with a program. However, the contents of these
registers do not affect ports programmed as the output ports.
Serial I/O2 function I/O
A-D conversion input
Sub-clock generating
circuit
Serial I/O1 function I/O
Serial I/O1 function I/O
Timer X function I/O
A-D conversion input
Timer Y function I/O
External interrupt input
External interrupt input
S
CMP2
output
External interrupt input
PWM output
A-D control register
A-D input selection register
CPU mode register
Serial I/O1 control register
Serial I/O1 control register
Timer XY mode register
A-D control register
A-D input selection register
Timer XY mode register
Interrupt edge selection
register
Interrupt edge selection
register
Serial I/O2 control register
Interrupt edge selection
register
PWM control register
(13)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
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