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參數(shù)資料
| 型號： | M38504M6-XXXFP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數(shù)： | 42/99頁 |
| 文件大?。?/td> | 1384K |
| 代理商： | M38504M6-XXXFP |
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42
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. A)
A-D CONVERTER
[A-D Conversion Registers (ADL, ADH)]
0035
16
, 0036
16
The A-D conversion registers are read-only registers that store the
result of an A-D conversion. Do not read these registers during an
A-D conversion.
[A-D Control Register (ADCON)] 0034
16
The A-D control register controls the A-D conversion process. Bits
0 to 2 select a specific analog input pin. By setting a value to these
bits, when bit 0 of the A-D input selection register (address
0037
16
) is
“
0
”
, P3
0
/AN
0
-P3
4
/AN
4
can be selected, and when bit 0
of the A-D input selection register is
“
1
”
, P0
4
/AN
5
-P0
7
/AN
8
can be
selected.
Bit 4 indicates the completion of an A-D conversion. The value of
this bit remains at
“
0
”
during an A-D conversion and changes to
“
1
”
when an A-D conversion ends. Writing
“
0
”
to this bit starts the A-D
conversion.
[A-D Input Selection Register (ADSEL)]
0037
16
The analog input port selection switch bit is assigned to bit 0 of the
A-D input selection register. When
“
0
”
is set to the analog input
port selection switch bit, P3
0
/AN
0
-P3
4
/AN
4
can be selected by the
analog input pin selection bits (b2, b1, b0) of the A-D control reg-
ister (address 0034
16
). When
“
1
”
is set to the analog input port
selection switch bit, P0
4
/AN
5
-P0
7
/AN
8
can be selected by the ana-
log input pin selection bits (b2, b1, b0) of the A-D control register
(address 0034
16
).
Comparison Voltage Generator
The comparison voltage generator divides the voltage between
AV
SS
and V
REF
into 1024 and outputs the divided voltages.
Channel Selector
The channel selector selects one of ports P3
0
/AN
0
to P3
4
/AN
4
,
P0
4
/AN
5
to P0
7
/AN
8
and inputs the voltage to the comparator.
Comparator and Control Circuit
The comparator and control circuit compare an analog input volt-
age with the comparison voltage, and the result is stored in the
A-D conversion registers. When an A-D conversion is completed,
the control circuit sets the A-D conversion completion bit and the
A-D interrupt request bit to
“
1
”
.
Note that because the comparator consists of a capacitor cou-
pling, set f(X
IN
) to 500 kHz or more during an A-D conversion.
When the A-D converter is operated at low-speed mode, f(X
IN
)
and f(X
CIN
) do not have the lower limit of frequency, because of
the A-D converter has a built-in self-oscillation circuit.
Fig. 42 Structure of A-D control register (spec. A)
Fig. 44 Structure of A-D conversion registers (spec. A)
Fig. 43 Structure of A-D input selection register (spec. A)
A
(
-
A
D
D
C
c
o
O
n
N
t
r
o
:
l
a
r
d
e
g
d
i
e
s
t
s
e
s
r
r
0
0
3
4
1
6
)
A
n
a
b
l
o
g
b
1
i
n
b
p
0
u
t
p
i
n
s
N
e
l
e
e
1
c
t
i
o
n
b
i
t
s
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
:
:
:
:
:
P
P
P
P
P
3
0
/
3
1
/
3
2
/
3
3
/
3
4
/
A
A
A
A
A
N
0
N
1
N
2
N
3
N
4
N
o
t
u
s
e
d
(
r
e
t
u
r
n
s
“
0
”
w
h
e
n
r
e
a
d
)
A
-
D
c
0
1
o
:
:
n
C
C
v
o
o
e
r
s
v
v
i
e
e
o
r
r
n
s
s
i
i
c
o
o
o
n
n
m
i
c
p
o
l
p
m
e
r
t
o
p
i
o
g
l
e
n
r
e
t
e
b
s
d
i
s
t
n
n
n
N
o
t
u
s
e
d
(
r
e
t
u
r
n
s
“
0
”
w
h
e
n
r
e
a
d
)
b
7
b0
2
o
t
o
o
o
o
r
r
r
r
P0
4
/AN
5
P0
5
/AN
6
P0
6
/AN
7
P0
7
/AN
8
––––––
N
o
t
e
2
N
o
t
e
s
1
:
T
(
T
(
h
a
h
a
i
s
d
s
d
i
r
i
r
s
e
s
e
s
s
s
s
e
s
e
s
l
0
l
e
0
e
c
0
c
0
t
e
7
1
e
d
3
7
1
d
6
)
w
6
)
w
h
i
s
h
i
e
e
s
n
“
0
n
“
1
b
”
b
”
i
t
0
o
f
t
h
e
A
-
D
i
n
p
u
t
s
e
l
e
c
t
i
o
n
r
e
g
i
s
t
e
r
d
i
d
3
t
.
2
:
i
t
0
o
f
t
h
e
A
-
D
i
n
p
u
t
s
e
l
e
c
t
i
o
n
r
e
g
i
s
t
e
r
.
A-D input selection register
(ADSEL: address 0037
16
)
Analog input port selection switch bit
0: P3
0
/AN
0
toP3
4
/AN
4 is selected as
analog input pin.
1: P0
4
/AN
5
to P0
7
/AN
8 is selected as
analog input pin.
Not used (returns
“
0
”
when read)
Fix this bit to
“
0
”
.
Not used (returns
“
0
”
when read)
Fix this bit to
“
0
”
.
b
7
b
0
1
0
-
R
b
i
t
a
r
d
e
a
a
d
d
i
d
n
g
r
e
(
e
s
s
0
0
3
6
1
b
6
b
e
f
o
r
e
0
0
3
5
1
6
)
(
A
d
d
r
e
s
s
0
0
3
6
1
6
)
(
A
d
d
r
e
s
s
0
0
3
5
1
6
)
8
-
b
i
t
r
e
a
d
i
n
g
(
R
e
a
d
o
n
b
l
y
a
d
d
r
e
s
s
0
0
3
5
1
6
)
(
A
d
d
r
e
s
s
0
0
3
5
1
6
)
b
0
8
7 b
6 b
5 b
4 b
3 b
2 b
1 b
0
7
b
0
b
9
b
7
b
N
o
t
e
:
T
a
h
t
e
r
h
a
i
d
g
h
n
-
g
o
.
r
d
e
r
6
b
i
t
s
o
f
a
d
d
r
e
s
s
0
0
3
6
1
6
b
e
c
o
m
e
“
0
”
e
i
9 b
8 b
7 b
6 b
5 b
4 b
3 b
2
7
b
0
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