參數(shù)資料
型號(hào)： M38507M8-XXXFP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁(yè)數(shù)： 60/99頁(yè)
文件大?。?/td> 1384K
代理商： M38507M8-XXXFP
60
3850 Group (Spec. H/A)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Functions To Inhibit Rewriting Flash Memory
Version
To prevent the contents of internal flash memory from being read
out or rewritten easily, this MCU incorporates a ROM code protect
function for use in parallel I/O mode and an ID code check func-
tion for use in standard serial I/O mode.
G
ROM Code Protect Function (in Parallel I/O Mode)
The ROM code protect function is the function to inhibit reading
out or modifying the contents of internal flash memory by using
the ROM code protect control (address FFDB
16
) in parallel I/O
mode. Figure 63 shows the ROM code protect control (address
FFDB
16
). (This address exists in the User ROM area.)
If one or both of the pair of ROM Code Protect Bits is set to “0”,
the ROM code protect is turned on, so that the contents of internal
flash memory are protected against readout and modification. The
ROM code protect is implemented in two levels. If level 2 is se-
lected, the flash memory is protected even against readout by a
shipment inspection LSI tester, etc. When an attempt is made to
select both level 1 and level 2, level 2 is selected by default.
If both of the two ROM Code Protect Reset Bits are set to “00”, the
ROM code protect is turned off, so that the contents of internal
flash memory can be read out or modified. Once the ROM code
protect is turned on, the contents of the ROM Code Protect Reset
Bits cannot be modified in parallel I/O mode. Use the serial I/O or
CPU rewrite mode to rewrite the contents of the ROM Code Pro-
tect Reset Bits.
Fig. 63 Structure of ROM code protect control
R
R
O
O
M
M
C
c
o
P
d
e
p
r
o
t
e
c
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
a
d
d
r
e
s
s
F
F
D
B
1
6
)
(
N
o
t
e
1
)
Reserved bits (
“
1
”
at read/write)
ROM code protect level 2 set bits (ROMCP2) (
Notes 2, 3
)
b3b2
0 0: Protect enabled
0 1: Protect enabled
1 0: Protect enabled
1 1: Protect disabled
ROM code protect reset bits
(
Note 4
)
b5b4
0 0: Protect removed
0 1: Protect set bits effective
1 0: Protect set bits effective
1 1: Protect set bits effective
ROM code protect level 1 set bits (ROMCP1) (
Note 2
)
b7b6
0 0: Protect enabled
0 1: Protect enabled
1 0: Protect enabled
1 1: Protect disabled
b
1
0
b
7
Notes 1
: This area is on the ROM in the mask ROM version.
2
: When ROM code protect is turned on, the internal flash memory is protected
against readout or modification in parallel I/O mode.
3
: When ROM code protect level 2 is turned on, ROM code readout by a shipment
inspection LSI tester, etc. also is inhibited.
4
: The ROM code protect reset bits can be used to turn off ROM code protect level 1
and ROM code protect level 2. However, since these bits cannot be modified in
parallel I/O mode, they need to be rewritten in standard serial I/O mode or CPU
rewrite mode.
1
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