參數(shù)資料
型號: M38858MC-XXXHP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PQFP80
封裝: 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80
文件頁數(shù): 64/105頁
文件大小: 1403K
代理商: M38858MC-XXXHP
3885 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
58
Fig. 52 Configuration of serialized IRQ control register
Register Explanation
The serialized IRQ function is configured and controlled by the se-
rialized IRQ request register (SERIRQ) and the serialized IRQ
control register (SERCON).
[Serialized IRQ control register (SERCON)] 001D16
Bit 0 : Serialized IRQ enable bit (SIRQEN )
This bit enables/disables the serialized IRQ interface. When this
bit is “1”, use of serialized IRQ is enabled. Then P87 functions as
IRQ/Data line (SERIRQ) and P47 functions as CLKRUN.
Output structure of CLKRUN pin becomes N-channel open drain.
Bit 1 : LPC clock restart enable bit (RUNEN )
Setting this bit to “1” enables clock restart with “L” output of
CLKRUN.
Bit 2 : LPC clock stop inhibition bit (SUPEN )
Setting this bit to “1” makes CLKRUN output change to “L” for in-
hibiting the clock stop.
Bit 3 : Hardware IRQ1 request bit (SEIR1)
When this bit is “1”, OBF0 status is directly connected to the IRQ1
frame.
Bit 4 : Hardware IRQ12 request bit (SEIR12 )
When this bit is “1”, OBF0 status is directly connected to IRQ12
frame.
Bit 5 : Hardware IRQx request bit (SEIRx )
When this bit is “1”, OBF1 status is directly connected to the IRQx
frame.
Bit 6 : IRQ1/IRQ12 disable bit (SCH0EN )
This bit controls whether the serialized IRQ channel 0 transfers
the IRQ1 and IRQ12 frame to the host or not.
Bit 7 : IRQx output polarity bit (SCH1POL)
This bit selects IRx frame output level.
Serialized IRQ control register
Bit name
Function
Bit symbol
W
R
Symbol
Address
When reset
SERCON
001D16
000000002
SIRQEN
Serialized IRQ enable bit
0 : Serialized IRQ disable
1 : Serialized IRQ enable
0 : Clock restart disable
1 : Clock restart enable
0 : Stop inhibition control disable
1 : Stop inhibition control enable
0 : No IRQ1 request
1 : OBF0 synchronized IRQ1 request
LPC clock restart enable bit
LPC clock stop inhibition bit
Hardware IRQ1 request bit
RUNEN
SUPEN
SEIR1
b7b6b5b4b3b2b1b0
Hardware IRQ12 request bit 0 : No IRQ12 request
1 : OBF0 synchronized IRQ12 request
SEIRx
Hardware IRQx request bit
0 : No IRQx request
1 : OBF1 synchronized IRQx request
SEIR12
SCH0EN
IRQ1/IRQ12 disable bit
0 : IRQ1/IRQ12 output enable
1 : IRQ1/IRQ12 output disable
IRQx output polarity bit0 : -Request Hiz-Hiz-Hiz
-No request L-H-Hiz
1 : -Request L-H-Hiz
-No request Hiz-Hiz-Hiz
SCH1POL
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