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參數(shù)資料
| 型號： | M38867H8A-AO1HP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | LJT 5C 5#16 PIN RECP |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數(shù)： | 24/110頁 |
| 文件大?。?/td> | 1601K |
| 代理商： | M38867H8A-AO1HP |
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24
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
TIMERS
The 3886 group has four timers: timer X, timer Y, timer 1, and
timer 2.
The division ratio of each timer or prescaler is given by 1/(n + 1),
where n is the value in the corresponding timer or prescaler latch.
All timers are count down. When the timer reaches “00
16
”, an un-
derflow occurs at the next count pulse and the corresponding
timer latch is reloaded into the timer and the count is continued.
When a timer underflows, the interrupt request bit corresponding
to that timer is set to “1”.
Timer 1 and Timer 2
The count source of prescaler 12 is the oscillation frequency di-
vided by 16. The output of prescaler 12 is counted by timer 1 and
timer 2, and a timer underflow sets the interrupt request bit.
Timer X and Timer Y
Timer X and Timer Y can each select in one of four operating
modes by setting the timer XY mode register.
(1) Timer Mode
The timer counts f(X
IN
)/16.
(2) Pulse Output Mode
Timer X (or timer Y) counts f(X
IN
)/16. Whenever the contents of
the timer reach “00
16
”, the signal output from the CNTR
0
(or
CNTR
1
) pin is inverted. If the CNTR
0
(or CNTR
1
) active edge se-
lection bit is “0”, output begins at “ H”.
If it is “1”, output starts at “L”. When using a timer in this mode, set
the corresponding port P5
4
( or port P5
5
) direction register to out-
put mode.
(3) Event Counter Mode
Operation in event counter mode is the same as in timer mode,
except that the timer counts signals input through the CNTR
0
or
CNTR
1
pin.
When the CNTR
0
(or CNTR
1
) active edge selection bit is “0”, the
rising edge of the CNTR
0
(or CNTR
1
) pin is counted.
When the CNTR
0
(or CNTR
1
) active edge selection bit is “1”, the
falling edge of the CNTR
0
(or CNTR
1
) pin is counted.
(4) Pulse Width Measurement Mode
If the CNTR
0
(or CNTR
1
) active edge selection bit is “0”, the timer
counts f(X
IN
)/16 while the CNTR
0
(or CNTR
1
) pin is at “H”. If the
CNTR
0
(or CNTR
1
) active edge selection bit is “1”, the timer
counts while the CNTR
0
(or CNTR
1
) pin is at “L”.
The count can be stopped by setting “1” to the timer X (or timer Y)
count stop bit in any mode. The corresponding interrupt request
bit is set each time a timer overflows.
The count source for timer Y in the timer mode or the pulse output
mode can be selected from either f(X
IN
)/16 or f(X
CIN
) by the timer
Y count source selection bit of the port control register 2 (bit 5 of
address 002F
16
).
Fig. 19 Structure of timer XY mode register
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