參數(shù)資料
型號(hào)： M38869MFA-XXXGP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁數(shù)： 12/110頁
文件大?。?/td> 1601K
代理商： M38869MFA-XXXGP
12
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Pin
Name
Input/Output
I/O Structure
Non-Port Function
Ref.No.
Table 4 I/O port function (1)
Related SFRs
I/O PORTS
The I/O ports have direction registers which determine the input/
output direction of each individual pin. Each bit in a direction reg-
ister corresponds to one pin, and each pin can be set to be input
port or output port.
When “0” is written to the bit corresponding to a pin, that pin be-
comes an input pin. When “1” is written to that bit, that pin
becomes an output pin.
If data is read from a pin which is set to output, the value of the
port output latch is read, not the value of the pin itself. Pins set to
input are floating. If a pin set to input is written to, only the port
output latch is written to and the pin remains floating.
When the P8 function select bit of the port control register 2 (ad-
dress 002F
16
) is set to “1”, read from address 0010
16
becomes
the port P4 input register, and read from address 0011
16
becomes
the port P7 input register.
As the particular function, value of P4
2
to P4
6
pins and P7
0
to P7
5
pins can be read regardless of setting direction registers, by read-
ing the port P4 input register (address 0010
16
) or the port P7 input
register (address 0011
16
) respectively.
P0
0
/P3
REF
P0
1
–P0
7
P1
0
–P1
7
P2
0
–P2
7
P3
0
/PWM
00
P3
1
/PWM
10
P3
2
–P3
7
P4
0
/X
COUT
P4
1
/X
CIN
P4
2
/INT
0
/
OBF
00
P4
3
/INT
1
/
OBF
01
P4
4
/R
X
D
P4
5
/T
X
D
P4
6
/S
CLK1
/OBF
10
P4
7
/S
RDY1
/S
1
Port P0
Port P1
Port P2
Port P3
Port P4
Input/output,
individual bits
CMOS compatible
input level
CMOS 3-state output
or N-channel open-
drain output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level or TTL
input level
CMOS 3-state output
or N-channel open-
drain output
Address low-order byte
output
Analog comparator
power source input pin
Address low-order byte
output
Address high-order
byte output
Data bus I/O
Control signal I/O
PWM output
Key-on wake up input
Comparator input
Control signal I/O
Key-on wake up input
Comparator input
Sub-clock generating
circuit
External interrupt input
Bus interface function
I/O
Serial I/O1 function in-
put
Serial I/O1 function out-
put
Serial I/O1 function I/O
Bus interface function
output
Serial I/O1 function out-
put
Bus interface function
input
CPU mode register
Port control register 1
Serial I/O2 control
register
CPU mode register
Port control register 1
CPU mode register
CPU mode register
Port control register 1
AD/DA control register
CPU mode register
Port control register 1
CPU mode register
Interrupt edge selection
register
Port control register 2
Serial I/O1 control
register
Port control register 2
Serial I/O1 control
register
UART control register
Port control register 2
Serial I/O1 control
register
Data bus buffer control
register
Port control register 2
Serial I/O1 control
register
Data bus buffer control
register
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
CMOS compatible
input level
CMOS 3-state output
(when selecting bus
interface function)
CMOS compatible
input level or TTL
input level
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