參數(shù)資料
型號(hào)： M38B43M2H-XXXXFP
廠商： Mitsubishi Electric Corporation
英文描述： OSC 3.3V SMT 7X5 CMOS
中文描述： 單芯片8位CMOS微機(jī)
文件頁(yè)數(shù)： 64/78頁(yè)
文件大小： 1214K
代理商： M38B43M2H-XXXXFP
64
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
NOTES ON PROGRAMMING
Processor Status Register
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1”. After a
reset, initialize flags which affect program execution. In particular, it
is essential to initialize the index X mode (T) and the decimal mode
(D) flags because of their effect on calculations.
Interrupts
The contents of the interrupt request bits do not change immediately
after they have been written. After writing to an interrupt request reg-
ister, execute at least one instruction before performing a BBC or
BBS instruction.
Decimal Calculations
To calculate in decimal notation, set the decimal mode flag (D) to
“1”, then execute an ADC or SBC instruction. Only the ADC and
SBC instructions yield proper decimal results. After executing an
ADC or SBC instruction, execute at least one instruction before ex-
ecuting a SEC, CLC, or CLD instruction.
In decimal mode, the values of the negative (N), overflow (V), and
zero (Z) flags are invalid.
Timers
If a value n (between 0 and 255) is written to a timer latch, the fre-
quency division ratio is 1/(n+1).
Multiplication and Division Instructions
The index X mode (T) and the decimal mode (D) flags do not affect
the MUL and DIV instruction.
The execution of these instructions does not change the contents of
the processor status register.
Ports
The contents of the port direction registers cannot be read. The
following cannot be used:
The data transfer instruction (LDA, etc.)
The operation instruction when the index X mode flag (T) is “1”
The addressing mode which uses the value of a direction register
as an index
The bit-test instruction (BBC or BBS, etc.) to a direction register
The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a
direction register.
Use instructions such as LDM and STA, etc., to set the port direction
registers.
Serial I/O
Using an external clock
When using an external clock, input “H” to the external clock input
pin and clear the serial I/O interrupt request bit before executing
serial I/O transfer and serial I/O automatic transfer.
Using an internal clock
When using an internal clock, set the synchronous clock to the in-
ternal clock, then clear the serial I/O interrupt request bit before ex-
ecuting a serial I/O transfer and serial I/O automatic transfer.
Automatic Transfer Serial I/O
When using the automatic transfer serial I/O mode of the serial I/O1,
set an automatic transfer interval as the following.
Otherwise the serial data might be incorrectly transmitted/received.
Set an automatic transfer interval for each 1-byte data transfer as
the following:
(1) Not using FLD controller
Keep the interval for
5 cycles or more of internal system clock
from clock rising of the last bit of 1-byte data.
(2) Using FLD controller
(a) Not using gradation display
Keep the interval for
12 cycles or more of internal system clock
from clock rising of the last bit of 1-byte data.
(b) Using gradation display
Keep the interval for
18 cycles or more of internal system clock
from clock rising of the last bit of 1-byte data.
A-D Converter
The comparator uses internal capacitors whose charge will be lost if
the clock frequency is too low.
Therefore, make sure that f(X
IN
) is at least on 250 kHz during an A-D
conversion.
Do not execute the STP or WIT instruction during an A-D conver-
sion.
Instruction Execution Time
The instruction execution time is obtained by multiplying the frequency
of the internal system clock by the number of cycles needed to ex-
ecute an instruction.
The number of cycles required to execute an instruction is shown in
the list of machine instructions.
The frequency of the internal system clock is the same of the X
IN
frequency in high-speed mode.
At STP Instruction Release
At the STP instruction release, all bits of the timer 12 mode register
are cleared.
The X
COUT
drivability selection bit (the CPU mode register) is set to
“1” (high drive) in order to start oscillating.
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM produc-
tion:
(1) Mask ROM Order Confirmation Form
(2) Mark Specification Form
(3) Data to be written to ROM, in EPROM form (three identical cop-
ies)
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