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參數(shù)資料
| 型號： | M38C89EFFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PQFP144 |
| 封裝： | 20 X 20 MM, 0.50 MM PITCH, PLASTIC, LQFP-144 |
| 文件頁數(shù)： | 13/54頁 |
| 文件大?。?/td> | 805K |
| 代理商： | M38C89EFFP |
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20
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C8 Group
TIMERS
The 38C8 group has five timers: timer X, timer Y, timer 1, timer 2, and
timer 3. Timer X and timer Y are 16-bit timers, and timer 1, timer 2,
and timer 3 are 8-bit timers.
All timers are down count timers. When the timer reaches “0016”, an
underflow occurs at the next count pulse and the corresponding timer
latch is reloaded into the timer and the count is continued. When a
timer underflows, the interrupt request bit corresponding to that timer
is set to “1”.
Read and write operation on 16-bit timer must be performed for both
high and low-order bytes. When reading a 16-bit timer, read the high-
order byte first. When writing to a 16-bit timer, write the low-order
byte first. The 16-bit timer cannot perform the correct operation when
reading during the write operation, or when writing during the read
operation.
Fig. 16 Timer block diagram
“10”
Timer Y stop
control bit
Falling edge detection
Period measure-
ment mode
Timer Y interrupt
request
Pulse width HL continuously
measurement mode
Rising edge detection
“00”,“01”,“11”
Timer Y operating
mode bits
Timer X interrupt
request
Timer X (low) (8)
Timer X (high) (8)
Timer X (low) latch (8)
Q
T
S
“0”
“1”
“10”
f(XIN)/16
(f(XCIN)/16 in low-speed mode)
“00”,“01”,“11”
CNTR0 active
edge switch bit
CNTR0 active
edge switch bit
Buzzer output mode
Timer 2 latch (8)
Timer 2 (8)
“1”
f(XCIN)/32
Timer 1 interrupt
request
Data bus
Internal clock
φ = XCIN divided by 2 in low-speed mode
CNTR0 interrupt
request
CNTR1 interrupt
request
Timer Y operating mode bits
“00”,“01”,“10”
“11”
“00”,“11”
“01”
Timer X operating
mode bits
P43/CNTR1/BEEP-
P42/CNTR0/BEEP+
“0”
“1”
Pulse width
measurement
mode
Buzzer output mode
P42 latch
P42 direction register
BEEP- valid bit
f(XCIN)
“0”
“1”
f(XIN)
Timer X count source
selection bit
f(XCIN)/32
Timer X operating
mode bits
Timer X stop control bit
Timer X write control bit
Timer X (high) latch (8)
CNTR1 active
edge switch bit
P43 direction register
P43 latch
f(XIN)/16
(f(XCIN)/16 in low-speed mode)
“1”
“0”
Timer Y (low) (8)
Timer Y (high) (8)
Timer Y (low) latch (8)
Timer Y (low) high (8)
f(XIN)/16
(f(XCIN)/16 in low-speed mode)
Timer 1 count source
selection bit
Timer 2 interrupt
request
Timer 3 interrupt
request
f(XIN)/16
(f(XCIN)/16 in low-speed mode)
Timer 2 count source
selection bit
Timer 2 write control bit
Timer 3 latch (8)
Timer 3 (8)
“0”
Timer 1 latch (8)
Timer 1 (8)
“1”
“0”
Timer 3 count source
selection bit
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