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參數(shù)資料
| 型號(hào)： | M38D24G4-XXXFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 6.25 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | 14 X 14 MM, 0.80 MM PITCH, PLASTIC, LQFP-64 |
| 文件頁(yè)數(shù)： | 29/136頁(yè) |
| 文件大?。?/td> | 2856K |
| 代理商： | M38D24G4-XXXFP |
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Rev.3.02
Apr 10, 2008
Page 124 of 131
REJ03B0177-0302
38D2 Group
Notes on Serial I/O1
Becaouse the operation of the serial I/O2 is as same as serial
I/O1, the following notes are written about the serial I/O1.
1. Write to Baud Rate Generator
Write to the baud rate generator while transmission/reception is
stopped.
2. Setting Sequence When Serial I/O1 Transmit
Interrupt Used
To use the serial I/O1 transmit interrupt, if the interrupt
occurrence synchronized with settings is not required, take the
following sequence:
(1) Set the serial I/O1 transmit interrupt enable bit (bit 2 of
interrupt control register 2 (address 003F16)) to “0”
(disabled).
(2) Set the transmit enable bit to “1”.
(3) After one or more instructions have been executed, set the
serial I/O1 transmit interrupt request bit (bit 2 of interrupt
request register 2 (address 003D16)) to “0” (no interrupt).
(4) Set the serial I/O1 transmit interrupt enable bit to “1”
(enabled).
<Reason>
When the transmit enable bit is set to “1”, the transmit buffer
empty flag (bit 0 of serial I/O1 status register) and the transmit
shift completion flag are set to “1”.
This allows an interrupt request to be generated regardless of
which interrupt occurrence source has been selected by the
transmit interrupt source selection bit (bit 3 of serial I/O1 control
register) and the serial I/O1 transmit interrupt request bit is set to
“1”.
3. Data Transmission Control Using Transmit Shift
Completion Flag
After transmit data is written to the transmit buffer register, the
transmit shift completion flag (bit 2 of serial I/O1 status register
(address 001916)) changes from “1” to “0” after a delay of 0.5 to
1.5 cycles of the system clock. Thus, after transmit data is written
to the transmit buffer register, note this delay when controlling
data transmission by referencing the transmit shift completion
flag.
4. Setting Serial I/O1 Control Register
Before setting the serial I/O1 control register again, first set both
the transmit enable bit and the receive enable bit to “0” and
initialize the transmission and reception circuits.
Fig. 103 Sequence of setting serial I/O1 control register
5. Pin Status After Transmission Completed
After transmission is completed, the TxD pin retains the level
when transmission is completed.
When the internal clock is selected in clock synchronous serial
I/O mode, the SCLK1 pin is set to “H”.
6. Serial I/O1 Enable Bit during Transmit Operation
During transmission, if the serial I/O1 enable bit (bit 7 of serial
I/O1 control register (address 001A16)) is set to “0”, the pin
function is set to an I/O port and the internal transmit operation
continues even though transmit data is not output externally.
Also, if the transmit buffer register is written in this state,
transmit operation starts internally. If the serial I/O1 enable bit is
set to “1” at this time, transmit data is output to the TxD pin from
that point.
7. Transmission
Control
External
Clock
Selected
During data transmission, if the external clock is selected as the
synchronous clock, set the transmit enable bit to “1” while SCLK1
is set to “H”. Also, write to the transmit buffer register while
SCLK1 is set to “H”.
8. Receive Operation in Clock Synchronous Serial I/O
Mode
During reception in clock synchronous serial I/O mode, set both
the transmit enable bit and the receive enable bit to “1”. Then
write dummy data to the transmit buffer register. When the
internal clock is selected as the synchronous clock, the
synchronous clock is output at this point and receive operation
starts. When the external clock is selected, reception is enabled at
this point and inputting the external clock starts transmit
operation.
The P55/TXD1 [P32/TxD2] pin outputs dummy data written in the
transmit buffer register.
9. Transmit/Receive Operation in Clock Synchronous
Serial I/O Mode
In clock synchronous serial I/O mode, set the transmit enable bit
and the receive enable bit to “0” simultaneously to stop
transmit/receive operations. If only one of the operations is
stopped, transmission and reception cannot be synchronized,
which will cause a bit error.
Set bits 0 to 3, and 6 of the serial I/O1 control
register.
Set both the transmit enable bit (TE) and the
receive enable bit (RE) to “0”
Set both the transmit enable bit (TE) and the receive
enable bit (RE), or one of them to “1”.
Settings can be made with
the LDM instruction at the
same time
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| M38D24G4XXXHP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
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| M38D24G5XXXHP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M38D24G6FP#U0 | 功能描述:IC 740/38D2 MCU QZ-ROM 80QFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:740/38000 標(biāo)準(zhǔn)包裝:250 系列:80C 核心處理器:8051 芯體尺寸:8-位 速度:16MHz 連通性:EBI/EMI，I²C，UART/USART 外圍設(shè)備:POR，PWM，WDT 輸入/輸出數(shù):40 程序存儲(chǔ)器容量:- 程序存儲(chǔ)器類型:ROMless EEPROM 大小:- RAM 容量:256 x 8 電壓 - 電源 (Vcc/Vdd):4.5 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:68-LCC（J 形引線） 包裝:帶卷 (TR) |
| M38D24G6HP#U0 | 功能描述:IC 740/38D2 MCU QZ-ROM 64LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:740/38000 標(biāo)準(zhǔn)包裝:250 系列:80C 核心處理器:8051 芯體尺寸:8-位 速度:16MHz 連通性:EBI/EMI，I²C，UART/USART 外圍設(shè)備:POR，PWM，WDT 輸入/輸出數(shù):40 程序存儲(chǔ)器容量:- 程序存儲(chǔ)器類型:ROMless EEPROM 大小:- RAM 容量:256 x 8 電壓 - 電源 (Vcc/Vdd):4.5 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:68-LCC（J 形引線） 包裝:帶卷 (TR) |
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