參數(shù)資料
型號: M38D24G4FP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 6.25 MHz, MICROCONTROLLER, PQFP64
封裝: 14 X 14 MM, 0.80 MM PITCH, PLASTIC, LQFP-64
文件頁數(shù): 30/138頁
文件大小: 2880K
代理商: M38D24G4FP
Rev.3.02
Apr 10, 2008
Page 123 of 131
REJ03B0177-0302
38D2 Group
10. Write to Timer X
(1) Timer X can select either writing data to both the latch and
the timer at the same time or writing data only by the timer
X write control bit (b3) in the timer X mode register
(address 002D16). When writing to the latch only, if a value
is written to the timer X address, the value is set into the
reload latch and the timer is updated at the next underflow.
After a reset release, if a value is written to the timer X
address, the value is set into the timer and the timer latch at
the same time, because they are written simultaneously.
When writing to the latch only, if the write timing to the
high-order reload latch and the underflow timing are almost
the same, the value is set into the timer and the timer latch at
the same time. At this time, count is stopped during write
operation to the high-order reload latch.
(2) Switch the frequency division or count source* while the
timer count is stopped.
*This also applies when the frequency divider output is selected
as the timer count source and the count source is switched in
conjunction with a transition between operating modes (on-
chip oscillator mode, XIN mode, or low-speed mode). Be
careful when changing settings in the CPU mode register.
11. Setting Timer X Mode Register
When PWM mode or IGBT output mode is set, be sure to set the
write control bit in the timer X mode register to “1” (writing to
latch only). After writing to the timer X register (high-order), the
contents of both registers are simultaneously reflected in the
output waveform at the next underflow.
12. Timer X Output Control Functions
To use the output control functions (INT1 and INT2), set the
levels of INT1 and INT2 to “H” for the falling edge active or to
“L” for the rising edge active before switching to IGBT output
mode.
13. CNTR0 Active Edge Selection
(1) Setting the CNTR0 active edge switch bits also affects the
interrupt active edge at the same time.
(2) When the pulse width is measured, set bit 7 of the CNTR0
active edge switch bits to “0”.
14. When Timer X Pulse Width Measurement Mode
Used
When timer X pulse mode measurement mode is used, enable the
event counter wind control data (bit 5 of timer X mode register
(address 002D16)) by setting to “0”.
<Reason>
If the event counter window control data (bit 5 of timer X mode
register (address 002D16)) is set to “1” (disabled) to
enable/disable the CNTR0 input, the input is not accepted after
the timer 1 underflow.
15. CNTR1 Active Edge Selection
Setting the CNTR1 active edge switch bits also affects the
interrupt active edge at the same time.
However, in pulse width HL continuous HL measurement mode,
the CNTR1 interrupt request is generated at both rising and
falling edges of the pin regardless of the settings of the CNTR1
active edge switch bits.
16. Read from/Write to Timer Y
(1) When reading from/writing to timer Y, read from/write to
both the high-order and low-order bytes of timer Y. To read
the value, read the high-order bytes first and the low-order
bytes next. To write the value, write the low-order bytes first
and the high-order bytes next.
Writing/reading should be preformed in 16-bit units. If
write/read operation is changed in progress, normal
operation will not be performed.
(2) Timer Y can select either writing data to both the latch and
the timer at the same time or writing data only by the timer
Y write control bit (b0) in the timer Y control register
(address 003916). When writing to the latch only, if a value
is written to the timer Y address, the value is set into the
reload latch and the timer is updated at the next underflow.
After a reset release, if a value is written to the timer Y
address, the value is set into the timer and the timer latch at
the same time, because they are written simultaneously.
When writing to the latch only, if the write timing to the
high-order reload latch and the underflow timing are almost
the same, the value is set into the timer and the timer latch at
the same time. At this time, count is stopped during write
operation to the high-order reload latch.
(3) Switch the frequency division or count source* while the
timer count is stopped.
*This also applies when the frequency divider output is selected
as the timer count source and the count source is switched in
conjunction with a transition between operating modes (on-
chip oscillator mode, XIN mode, or low-speed mode). Be
careful when changing settings in the CPU mode register.
17. Real time port control
When switching the setting of the real time port control bits
between valid and invalid, write to the timer Y mode register in
byte units with the LDM or STA instruction so that both bits are
switched at the same time. Also, before using this function, set
the P46 and P47 port direction registers to output.
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