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參數(shù)資料
| 型號(hào)： | M38D29GC-XXXHP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 6.25 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | 10X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-64 |
| 文件頁(yè)數(shù)： | 67/138頁(yè) |
| 文件大?。?/td> | 2880K |
| 代理商： | M38D29GC-XXXHP |
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Rev.3.02
Apr 10, 2008
Page 32 of 131
REJ03B0177-0302
38D2 Group
Frequency Divider For Timer
Timer 1, timer 2, timer 3 and timer 4 have the frequency divider
for the count source. The count source of the frequency divider is
switched to XIN, XCIN, or the on-chip oscillator OCO divided by
4 in the on-chip oscillator mode by the CPU mode register. The
frequency divider is controlled by each timer division ratio
selection bit. The division ratio can be selected from as follows;
1/1, 1/2, 1/16, 1/256 of f(XIN), f(XCIN) or f(OCO)/4. Switch the
frequency division or count source* while the timer count is
stopped.
*This also applies when the frequency divider output is selected
as the timer count source and the count source is switched in
conjunction with a transition between operating modes (on-
chip oscillator mode, XIN mode, or low-speed mode). Be
careful when changing settings in the CPU mode register.
Timer 1, Timer 2
The count source for timer 1 and timer 2 can be set using the
timer 12 mode register. XCIN may be selected as the count
source. If XCIN is selected, count operation is possible regardless
of whether or not the XIN input oscillator or the on-chip oscillator
is operating. In addition, the timer 12 mode register can be used
to output from the P36/T2OUT pin a signal to invert the polarity
every time timer 2 underflows.
At reset, all bits of the timer 12 mode register are set to “0”, timer
1 is set to “FF16”, and timer 2 is set to “0116”.
When executing the STP instruction, previously set the wait time
at return.
Timer 3, Timer 4
The count sources of timer 3 and timer 4 can be selected by
setting the timer 34 mode register. Also, by the timer 34 mode
register, each time timer 3 or timer 4 underflows, the signal of
which polarity is inverted can be output from P52/T3OUT pin or
P53/T4OUT pin.
Timer 3 PWM0 Mode, Timer 4 PWM1 Mode
A PWM rectangular waveform corresponding to the 10-bit
accuracy can be output from the P52/PWM0 pin and P53/PWM1
pin by setting the timer 34 mode register and PWM01 register
(refer to Figure 24).
One output pulse is the short interval. Four output pulses are the
long interval. The “n” is the value set in the timer 3 (address
002216) or the timer 4 (address 002316). The “ts” is one period of
timer 3 or timer 4 count source. “H” width of the short interval is
obtained by n
× ts.
However, in the long interval, “H” width of output pulse is
extended for ts which is set by the PWM01 register (address
002416).
<Notes on Timer 1 to Timer 4>
(1) Timer 3 PWM0 Mode, Timer 4 PWM1 Mode
When PWM output is suspended after starting PWM output,
depending on the level of the output pulse at that time to
resume an output, the delay of the one section of the short
interval may be needed.
Stop at “H”: No output delay
Stop at “L”: Output is delayed time of 256
× ts
In the PWM mode, the follows are performed every cycle of
the long interval (4
× 256 × ts).
Generation of timer 3, timer 4 interrupt requests
Update of timer 3, timer 4
(2) Write to Timer 2, Timer 3, Timer 4
When writing to the latch only, if the write timing to the reload
latch and the underflow timing are almost the same, the value is
set into the timer and the timer latch at the same time. In this
time, counting is stopped during writing to the reload latch.
Fig. 24 Waveform of PWM0 and PWM1
Output waveform of timer 3 PWM0 or timer 4 PWM1
n: Setting value of timer 3 or timer 4
ts: One period of timer 3 count source or timer 4 count source
PWM01 register (address 002416) : 2-bit value corresponding to PWM0 (bits 0, 1) or PWM1 (bits 2, 3)
256
×
ts
256
×
ts
256
×
ts
256
×
ts
n
× ts
n
× ts
n
× ts
n
× ts
n
× ts
n
× ts
n
× ts
n
× ts
n
× ts
n
× ts
PWM01 register = “002”
PWM01 register = “012”
PWM01 register = “102”
PWM01 register = “112”
(n+1)
× ts
(n+1)
× ts
(n+1)
× ts
(n+1)
× ts
(n+1)
× ts
(n+1)
× ts
Short interval
Long interval
4
× 256 ×
ts
Interrupt request
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
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