參數(shù)資料
型號： M38D29GC-XXXHP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 6.25 MHz, MICROCONTROLLER, PQFP64
封裝： 10X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-64
文件頁數(shù)： 75/136頁
文件大?。?/td> 2856K
代理商： M38D29GC-XXXHP
Rev.3.02
Apr 10, 2008
Page 43 of 131
REJ03B0177-0302
38D2 Group
Fig. 35 Structure of serial I/O related registers
b7
b0
b7
b0
b7
b0
BRG count source selection bit (CSS)
0:
φSOURCE
1:
φSOURCE/4
Serial I/O synchronous clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronous
serial I/O is selected.
BRG output divided by 16 when UART is selected.
1: External clock input when clock synchronous serial
I/O is selected.
External clock input divided by 16 when UART is selected.
SRDY output enable bit (SRDY)
0: P57 [P30] pin operates as ordinary I/O pin
1: P57 [P30] pin operates as SRDY output pin
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Serial I/O mode selection bit (SIOM)
0: Clock asynchronous (UART) serial I/O
1: Clock synchronous serial I/O
Serial I/O enable bit (SIOE)
0: Serial I/O disabled
(pins P54 [P30] to P57 [P33] operate as ordinary I/O pins)
1: Serial I/O enabled
(pins P54 [P30] to P57 [P33] operate as serial I/O pins)
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
Transmit shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
Overrun error flag (OE)
0: No error
1: Overrun error
Parity error flag (PE)
0: No error
1: Parity error
Framing error flag (FE)
0: No error
1: Framing error
Summing error flag (SE)
0: (OE) U (PE) U (FE)=0
1: (OE) U (PE) U (FE)=1
Not used (returns “1” when read)
Serial I/O control register
(SIO1CON : address 001A16)
[SIO2CON : address 001F16]
Serial I/O status register
(SIO1STS : address 001916)
[SIO2STS : address 001E16]
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P55/TXD1 [P32/TxD2] P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open drain output (in output mode)
Not used (return “1” when read)
UART control register
(UART1CON : address 001B16)
[UART2CON : address 0FF116]
( ) : For Serial I/O1
[ ] : For Serial I/O2
φ SOURCE: represents the supply source of internal clock φ.
XIN input: in the frequency/2, 4 or 8 mode,
Internal on-chip oscillator divided by 4 in the on-chip
oscillator mode, and Sub clock in the low-speed mode.
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