參數(shù)資料
型號(hào)： M40Z300AVMQ6E
廠商： 意法半導(dǎo)體
英文描述： 3V NVRAM Supervisor for Up to 8 LPSRAMs
中文描述： 3V的NVRAM中監(jiān)多達(dá)8個(gè)LPSRAMs
文件頁(yè)數(shù)： 4/20頁(yè)
文件大小： 131K
代理商： M40Z300AVMQ6E
M40Z300AV
4/20
DESCRIPTION
The M40Z300AV NVRAM SUPERVISOR is a self-
contained device which converts a standard low-
power SRAM into a non-volatile memory. A preci-
sion voltage reference and comparator monitors
the V
CC
input for an out-of-tolerance condition.
When an invalid V
CC
condition occurs, the condi-
tioned chip enable outputs (E1
CON
to E4
CON
) are
forced inactive to write-protect the stored data in
the SRAM. During a power failure, the SRAM is
switched from the V
CC
pin to the lithium cell within
the SNAPHAT
to provide the energy required for
data retention. On a subsequent power-up, the
SRAM remains write protected until a valid power
condition returns.
The 28-pin, 330mil SOIC provides sockets with
gold plated contacts for direct connection to a sep-
arate SNAPHAT housing containing the battery.
The SNAPHAT housing has gold plated pins
which mate with the sockets, ensuring reliable
connection. The housing is keyed to prevent im-
proper insertion. This unique design allows the
SNAPHAT battery package to be mounted on top
of the SOIC package after the completion of the
surface mount process which greatly reduces the
board manufacturing process complexity of either
directly soldering or inserting a battery into a sol-
dered holder. Providing non-volatility becomes a
“SNAP.” The 16-pin SOIC provides battery pins for
an external user-supplied battery.
Insertion of the SNAPHAT housing after reflow
prevents potential battery damage due to the high
temperatures required for device surface-mount-
ing. The SNAPHAT housing is also keyed to pre-
vent reverse insertion.
The 28-pin SOIC and battery packages are
shipped separately in plastic anti-static tubes or in
Tape & Reel form. For the 28-lead SOIC, the bat-
tery/crystal package (e.g., SNAPHAT) part num-
ber
is
“M4ZXX-BR00SH”
13., page 18
).
Caution:
Do not place the SNAPHAT battery top
in conductive foam, as this will drain the lithium
button-cell battery.
(see
Table
Figure 3. Logic Diagram
Note: 1. For 16-pin SOIC package only.
2. THS pin must be connected to V
SS
.
Table 1. Signal Names
Note: 1. THS pin must be connected to V
SS
.
2. For M40Z300AV, B– must be connected to the negative
battery terminal only (not to Pin 8, V
SS
).
AI08893
THS
(2)
VCC
M40Z300AV
BL
VSS
E
VOUT
B
A
E1CON
E2CON
E3CON
E4CON
RST
B+
(1)
B–
(1)
THS
(1)
Threshold Select Input
E
Chip Enable Input
E1
CON
- E4
CON
Conditioned Chip Enable
Output
A, B
Decoder Inputs
RST
Reset Output (Open Drain)
BL
Battery Low Output (Open
Drain)
V
OUT
Supply Voltage Output
V
CC
Supply Voltage
V
SS
Ground
B +
Positive Battery Pin
B –
(2)
Negative Battery Pin
NC
Not Connected Internally
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相關(guān)代理商/技術(shù)參數(shù)
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