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參數(shù)資料
| 型號： | M40Z300MH6TR |
| 廠商： | 意法半導體 |
| 英文描述： | 5V or 3V NVRAM Supervisor for Up to 8 LPSRAMs |
| 中文描述： | 5V或3V NVRAM中監(jiān)多達8個LPSRAMs |
| 文件頁數(shù)： | 7/21頁 |
| 文件大?。?/td> | 132K |
| 代理商： | M40Z300MH6TR |
7/21
M40Z300, M40Z300W
OPERATION
The M40Z300/W, as shown in
Figure 7., page 6
,
can control up to four (eight, if placed in parallel)
standard low-power SRAMs. These SRAMs must
be configured to have the chip enable input dis-
able all other input signals. Most slow, low-power
SRAMs are configured like this, however many
fast SRAMs are not. During normal operating con-
ditions, the conditioned chip enable (E1
CON
to
E4
CON
) output pins follow the chip enable (E) input
pin with timing shown in
Figure 8., page 8
and
Ta-
ble 7., page 14
. An internal switch connects V
CC
to V
OUT
. This switch has a voltage drop of less
than 0.3V (I
OUT1
).
When V
CC
degrades during a power failure,
E1
CON
to E4
CON
are forced inactive independent
of E. In this situation, the SRAM is unconditionally
write protected as V
CC
falls below an out-of-toler-
ance threshold (V
PFD
). For the M40Z300 the pow-
er fail detection value associated with V
PFD
is
selected by the Threshold Select (THS) pin and is
shown in
Table 6., page 12
. For the M40Z300W,
the THS pin selects both the supply voltage and
V
PFD
(also shown in
Table 6., page 12
).
Note:
In either case, THS pin must be connected
to either V
SS
or V
OUT
.
If chip enable access is in progress during a power
fail detection, that memory cycle continues to com-
pletion before the memory is write protected. If the
memory cycle is not terminated within time t
WPT
,
E1
CON
to E4
CON
are unconditionally driven high,
write protecting the SRAM. A power failure during
a WRITE cycle may corrupt data at the currently
addressed location, but does not jeopardize the
rest of the SRAM's contents. At voltages below
V
PFD
(min), the user can be assured the memory
will be write protected within the Write Protect
Time (t
WPT
) provided the V
CC
fall time exceeds t
F
(see
Figure 8., page 8
).
As V
CC
continues to degrade, the internal switch
disconnects V
CC
and connects the internal battery
to V
OUT
. This occurs at the switchover voltage
(V
SO
). Below the V
SO
, the battery provides a volt-
age V
OHB
to the SRAM and can supply current
I
OUT2
(see
Table 6., page 12
).
When V
CC
rises above V
SO
, V
OUT
is switched
back to the supply voltage. Outputs E1
CON
to
E4
CON
are held inactive for t
CER
(120ms maxi-
mum) after the power supply has reached V
PFD
,
independent of the E input, to allow for processor
stabilization (see
Figure 12., page 13
).
Two to Four Decode
The M40Z300/W includes a 2 input (A, B) decoder
which allows the control of up to 4 independent
SRAMs. The Truth Table for these inputs is shown
in
Table 2.
Table 2. Truth Table
Inputs
Outputs
E
B
A
E1
CON
E2
CON
E3
CON
E4
CON
H
X
X
H
H
H
H
L
L
L
L
H
H
H
L
L
H
H
L
H
H
L
H
L
H
H
L
H
L
H
H
H
H
H
L
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相關代理商/技術參數(shù) |
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| M40Z300MQ | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:NVRAM CONTROLLER for up to EIGHT LPSRAM |
| M40Z300MQ1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:NVRAM CONTROLLER for up to EIGHT LPSRAM |
| M40Z300MQ1E | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5 V or 3 V NVRAM supervisor for up to 8 LPSRAMs |
| M40Z300MQ1F | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5V or 3V NVRAM supervisor for up to 8 LPSRAMs |
| M40Z300MQ1TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:NVRAM CONTROLLER for up to EIGHT LPSRAM |
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