參數(shù)資料
型號(hào)： M44C892
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 4 MHz, MICROCONTROLLER, PDSO20
封裝： SSO-20
文件頁(yè)數(shù)： 55/84頁(yè)
文件大小： 643K
代理商： M44C892
M44C892
M44C892
M44C092
Rev. A5, 14-Dec-01
59 (84)
Serial Interface Registers
Serial Interface Control Register 1 (SIC1)
Auxiliary register address: ’9’hex
Bit 3
Bit 2
Bit 1
Bit 0
SIC1
SIR
SCD
SCS1
SCS0
Reset value: 1111b
SIR
Serial Interface Reset
SIR = 1, SSI inactive
SIR = 0, SSI active
SCD
Serial Clock Direction
SCD = 1, SC line used as output
SCD = 0, SC line used as input
Note: This bit has to be set to ’1’ during the I2C mode and the Timer 3 mode 10 or 11
SCS1
Serial Clock source Select bit 1
SCS1
SCS0
Internal Clock for SSI
SCS0
Serial Clock source Select bit 0
1
1
SYSCL / 2
1
0
T1OUT / 2
Note: with SCD = ’0’ the bits SCS1
0
1
POUT / 2
and SCS0 are insignificant
0
0
TOG2 / 2
In Transmit mode (SDD = 1) shifting starts only if the transmit buffer has been loaded (SRDY = 1).
Setting SIR-bit loads the contents of the shift register into the receive buffer (synchronous 8-bit mode only).
In I2C modes, writing a 0 to SIR generates a start condition and writing a 1 generates a stop condition.
Serial Interface Control Register 2 (SIC2)
Auxiliary register address: ’A’hex
Bit 3
Bit 2
Bit 1
Bit 0
SIC2
MSM
SM1
SM0
SDD
Reset value: 1111b
MSM
Modular Stop Mode
MSM = 1, modulator stop mode disabled (output masking off)
MSM = 0, modulator stop mode enabled (output masking on) – used in modulation modes for
generating bit streams which are not sub-multiples of 8 bit.
SM1
Serial Mode control bit 1 Mode
SM1
SM0
SSI Mode
SM0
Serial Mode control bit 0
1
1
1
8-bit NRZ-Data changes with the rising edge of SC
2
1
0
8-bit NRZ-Data changes with the falling edge of SC
3
0
1
9-bit two-wire I2C compatible
4
0
0
8-bit two-wire pseudo I2C compatible (no
acknowledge)
SDD
Serial Data Direction
SDD = 1, transmit mode – SD line used as output (transmit data). SRDY is set by a transmit buffer
write access.
SDD = 0, receive mode –
SD line used as input (receive data). SRDY is set by a receive buffer
read access
Note: SDD controls port directional control and defines the reset function for the SRDY–flag
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