參數(shù)資料
型號： M466F0804DT1-L
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 8M x 64 DRAM SODIMM Using 4Mx16, 4K Refresh 3.3V, Low power/Self-Refresh
中文描述： 8米× 64內(nèi)存的SODIMM使用4Mx16，低功耗4K的刷新3.3 /自刷新
文件頁數(shù)： 1/20頁
文件大?。?/td> 303K
代理商： M466F0804DT1-L
DRAM MODULE
M466F0804DT1-L
REV. 0.1 Oct. 2000
M466F0804DT1-L EDO Mode
8M x 64 DRAM SODIMM Using 4Mx16, 4K Refresh 3.3V, Low power/Self-Refresh
The Samsung M466F0804DT1-L is a 8Mx64bits Dynamic
RAM high density memory module. The Samsung
M466F0804DT1-L consists of eight CMOS 4Mx16bits DRAMs
in TSOP 400mil packages and a 2K EEPROM in 8-pin
TSSOP package mounted on a 144-pin glass-epoxy sub-
strate. A 0.1uF decoupling capacitor is mounted on the
printed circuit board for each DRAM. The M466F0804DT1-L
is a Small Out-line Dual in-line Memory Module and is
intended for mounting into 144 pin edge connector sockets.
Part Identification
- M466F0804DT1-L(4096 cycles/128ms, TSOP, L-ver)
Extended Data Out Mode Operation
New JEDEC standard proposal with EEPROM
Serial Presense Detect with EEPROM
CAS-before-RAS Refresh capability
Self -refresh capability
RAS-only and Hidden refresh capability
LVTTL compatible inputs and outputs
Single +3.3V
±
0.3V power supply
PCB : Height(1000mil), double sided component
GENERAL DESCRIPTION
FEATURES
PERFORMANCE RANGE
t
RAC
Speed
t
CAC
t
RC
t
HPC
-L50
50ns
13ns
84ns
20ns
-L60
60ns
15ns
104ns
25ns
PIN CONFIGURATIONS
Pin
Front
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
DQ12
48
Back
V
SS
DQ32
DQ33
DQ34
DQ35
V
CC
DQ36
DQ37
DQ38
DQ39
V
SS
CAS4
CAS5
V
CC
A3
A4
A5
V
SS
DQ40
DQ41
DQ42
DQ43
V
CC
DQ44
Pin
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
Front
DQ13
DQ14
DQ15
V
SS
RSVD
RSVD
RFU
V
CC
RFU
W
RAS0
RAS1
OE
V
SS
RSVD
RSVD
V
CC
DQ16
DQ17
DQ18
DQ19
V
SS
DQ20
DQ21
Pin
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
Back
DQ45
DQ46
DQ47
V
SS
RSVD
RSVD
RFU
V
CC
RFU
RFU
RFU
RFU
RFU
V
SS
RSVD
RSVD
V
CC
DQ48
DQ49
DQ50
DQ51
V
SS
DQ52
DQ53
Pin
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
Front
DQ22
DQ23
V
CC
A6
A8
V
SS
A9
A10
V
CC
CAS2
CAS3
V
SS
DQ24
DQ25
DQ26
DQ27
V
CC
DQ28
DQ29
DQ30
DQ31
V
SS
SDA
V
CC
Pin
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
Back
DQ54
DQ55
V
CC
A7
A11
V
SS
NC
NC
V
CC
CAS6
CAS7
Vss
DQ56
DQ57
DQ58
DQ59
V
CC
DQ60
DQ61
DQ62
DQ63
Vss
SCL
V
CC
V
SS
DQ0
DQ1
DQ2
DQ3
V
CC
DQ4
DQ5
DQ6
DQ7
V
SS
CAS0
CAS1
V
CC
A0
A1
A2
V
SS
DQ8
DQ9
DQ10
DQ11
V
CC
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
PIN NAMES
Pin Name
A0 to
DQ0 - DQ63
W
OE
RAS0, RAS1
CAS0 - CAS7
V
CC
V
SS
NC
SDA
SCL
RSVD
RFU
Function
Address Inputs
Data In/Out
Read/Write Enable
Output Enable
Row Address Strobe
Column Address Strobe
Power(+3.3V)
Ground
No Connection
Serial Address / Data I/O
Serial Clock
Reserved Use
Reserved for Future Use
相關(guān)PDF資料
PDF描述
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