參數(shù)資料
型號： M470T6554CZ3-CLD5
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： DDR2 Unbuffered SODIMM 200pin Unbuffered SODIMM based on 512Mb C-die 64bit Non-ECC
中文描述： 內(nèi)存緩沖的SODIMM 200pin緩沖的SODIMM上的512Mb基于C模具64非ECC
文件頁數(shù)： 14/18頁
文件大小： 328K
代理商： M470T6554CZ3-CLD5
Rev. 1.2 Aug. 2005
256MB, 512MB, 1GB Unbuffered SODIMMs
DDR2 SDRAM
Parameter
Symbol
DDR2-800
DDR2-667
DDR2-533
DDR2-400
Units
Notes
min
max
min
max
min
max
min
max
DQS input low pulse width
tDQSL
0.35
x
0.35
x
0.35
x
0.35
x
tCK
DQS falling edge to CK setup time
tDSS
0.2
x
0.2
x
0.2
x
0.2
x
tCK
DQS falling edge hold time from CK
tDSH
0.2
x
0.2
x
0.2
x
0.2
x
tCK
Mode register set command cycle time
tMRD
2
x
2
x
2
x
2
x
tCK
Write postamble
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCK
Write preamble
tWPRE
0.35
x
0.35
x
0.35
x
0.35
x
tCK
Address and control input hold time
tIH(base)
250
x
275
x
375
x
475
x
ps
Address and control input setup time
tIS(base)
175
x
200
x
250
x
350
x
ps
Read preamble
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
tCK
Read postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCK
Active to active command period for 1KB page
size products
tRRD
7.5
x
7.5
x
7.5
x
7.5
x
ns
Active to active command period for 2KB page
size products
tRRD
10
x
10
x
10
x
10
x
ns
Four Activate Window for 1KB page size
products
tFAW
35
37.5
37.5
37.5
ns
Four Activate Window for 2KB page size
products
tFAW
45
50
50
50
ns
CAS to CAS command delay
tCCD
2
x
2
2
2
tCK
Write recovery time
tWR
15
x
15
x
15
x
15
x
ns
Auto precharge write recovery + precharge
time
tDAL
WR+tRP
x
WR+tRP
x
WR+tRP
x
WR+tRP
x
tCK
Internal write to read command delay
tWTR
7.5
7.5
x
7.5
x
10
x
ns
Internal read to precharge command delay
tRTP
7.5
7.5
7.5
7.5
ns
Exit self refresh to a non-read command
tXSNR
tRFC + 10
tRFC + 10
tRFC + 10
tRFC + 10
ns
Exit self refresh to a read command
tXSRD
200
x
200
200
200
tCK
Exit precharge power down to any non-read
command
tXP
2
x
2
x
2
x
2
x
tCK
Exit active power down to read command
tXARD
2
x
2
x
2
x
2
x
tCK
Exit active power down to read command
(slow exit, lower power)
tXARDS
8 - AL
7 - AL
6 - AL
6 - AL
tCK
CKE minimum pulse width
(high and low pulse width)
tCKE
3
3
3
3
tCK
ODT turn-on delay
tAOND
2
2
2
2
2
2
2
2
tCK
ODT turn-on
tAON
tAC(min)
tAC(max)
+ 0.7
tAC(min)
tAC(max)
+0.7
tAC(min)
tAC(max)
+1
tAC(min)
tAC(max)
+1
ns
ODT turn-on(Power-Down mode)
tAONPD
tAC(min)+
2
2tCK +
tAC(max)
+1
tAC(min)+
2
2tCK+tAC
(max)+1
tAC(min)+
2
2tCK+tA
C(max)+
1
tAC(min)+
2
2tCK+tAC
(max)+1
ns
ODT turn-off delay
tAOFD
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
tCK
ODT turn-off
tAOF
tAC(min)
tAC(max)
+ 0.6
tAC(min)
tAC(max)
+ 0.6
tAC(min)
tAC(max)+
0.6
tAC(min)
tAC(max)+
0.6
ns
ODT turn-off (Power-Down mode)
tAOFPD
tAC(min)+
2
2.5tCK +
tAC(max)
+1
tAC(min)+
2
2.5tCK+
tAC(max)
+1
tAC(min)+
2
2.5tCK+
tAC(max)
+1
tAC(min)+
2
2.5tCK+
tAC(max)
+1
ns
ODT to power down entry latency
tANPD
3
3
3
3
tCK
ODT power down exit latency
tAXPD
8
8
8
8
tCK
OCD drive mode output delay
tOIT
0
12
0
12
0
12
0
12
ns
Minimum time clocks remains ON after CKE
asynchronously drops LOW
tDelay
tIS+tCK
+tIH
tIS+tCK
+tIH
tIS+tCK
+tIH
tIS+tCK
+tIH
ns
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M470T6554CZ3-CLE7 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR2 Unbuffered SODIMM 200pin Unbuffered SODIMM based on 512Mb C-die 64bit Non-ECC
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